Nicholas Piggin <npig...@gmail.com> writes:

> Processors that support KVM HV do not require read-modify-write of
> the CTRL SPR to set/clear their thread's runlatch. Just write 1 or 0
> to it.
>
> Signed-off-by: Nicholas Piggin <npig...@gmail.com>

Reviewed-by: Fabiano Rosas <faro...@linux.ibm.com>

> ---
>  arch/powerpc/kvm/book3s_hv.c            |  2 +-
>  arch/powerpc/kvm/book3s_hv_rmhandlers.S | 15 ++++++---------
>  2 files changed, 7 insertions(+), 10 deletions(-)
>
> diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
> index f0ad3fb2eabd..1c5b81bd02c1 100644
> --- a/arch/powerpc/kvm/book3s_hv.c
> +++ b/arch/powerpc/kvm/book3s_hv.c
> @@ -4058,7 +4058,7 @@ static void load_spr_state(struct kvm_vcpu *vcpu)
>        */
>
>       if (!(vcpu->arch.ctrl & 1))
> -             mtspr(SPRN_CTRLT, mfspr(SPRN_CTRLF) & ~1);
> +             mtspr(SPRN_CTRLT, 0);
>  }
>
>  static void store_spr_state(struct kvm_vcpu *vcpu)
> diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S 
> b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
> index 7fa0df632f89..070e228b3c20 100644
> --- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
> +++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
> @@ -775,12 +775,11 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
>       mtspr   SPRN_AMR,r5
>       mtspr   SPRN_UAMOR,r6
>
> -     /* Restore state of CTRL run bit; assume 1 on entry */
> +     /* Restore state of CTRL run bit; the host currently has it set to 1 */
>       lwz     r5,VCPU_CTRL(r4)
>       andi.   r5,r5,1
>       bne     4f
> -     mfspr   r6,SPRN_CTRLF
> -     clrrdi  r6,r6,1
> +     li      r6,0
>       mtspr   SPRN_CTRLT,r6
>  4:
>       /* Secondary threads wait for primary to have done partition switch */
> @@ -1203,12 +1202,12 @@ guest_bypass:
>       stw     r0, VCPU_CPU(r9)
>       stw     r0, VCPU_THREAD_CPU(r9)
>
> -     /* Save guest CTRL register, set runlatch to 1 */
> +     /* Save guest CTRL register, set runlatch to 1 if it was clear */
>       mfspr   r6,SPRN_CTRLF
>       stw     r6,VCPU_CTRL(r9)
>       andi.   r0,r6,1
>       bne     4f
> -     ori     r6,r6,1
> +     li      r6,1
>       mtspr   SPRN_CTRLT,r6
>  4:
>       /*
> @@ -2178,8 +2177,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_TM)
>        * Also clear the runlatch bit before napping.
>        */
>  kvm_do_nap:
> -     mfspr   r0, SPRN_CTRLF
> -     clrrdi  r0, r0, 1
> +     li      r0,0
>       mtspr   SPRN_CTRLT, r0
>
>       li      r0,1
> @@ -2198,8 +2196,7 @@ kvm_nap_sequence:               /* desired LPCR value 
> in r5 */
>
>       bl      isa206_idle_insn_mayloss
>
> -     mfspr   r0, SPRN_CTRLF
> -     ori     r0, r0, 1
> +     li      r0,1
>       mtspr   SPRN_CTRLT, r0
>
>       mtspr   SPRN_SRR1, r3

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