Pali Rohár <p...@kernel.org> writes: > Hello! > > I started playing with PowerPC e500 architecture, it is something really > new for me and I suspect that I found a bug in U-Boot code which > configures L2 cache as initial SRAM (L2 with locked lines). > > U-Boot code for the first half of L2 cache sets Caching-inhibited > (MAS2_I) in TLB and for second half of L2 cache it unsets this bit. > And I think that this is a bug as it seems strange if one half of L2 > should be mapped differently than second half. > > I wrote about it email to U-Boot mailing list: > https://lore.kernel.org/u-boot/20220413092633.gmz4rqpiha4rwecb@pali/ > > I discussed about it on U-Boot IRC channel and developers suggested me > to write on Linux PowerPC mailing list as there could be more skilled > people. > > Michael, or anybody else, could you help me with this? Do you know if L2 > SRAM entry in TLB for e500v2 / BookE architecture should have MAS2_I bit > set or not?
Sorry I don't know those sort of low-level details for Freescale machines. Hopefully some former Freescale person will remember and reply here. It's also possible that Linux ignores what U-Boot did and sets it up itself, have you looked at the Linux code? cheers
