On Wed Aug 24, 2022 at 12:05 PM AEST, Rohan McLure wrote: > The common interrupt handler prologue macro and the bad_stack > trampolines include consecutive sequences of register saves, and some > register clears. Neaten such instances by expanding use of the SAVE_GPRS > macro and employing the ZEROIZE_GPR macro when appropriate. > > Also simplify an invocation of SAVE_GPRS targetting all non-volatile > registers to SAVE_NVGPRS. > Reviewed-by: Nicholas Piggin <npig...@gmail.com>
> Signed-off-by: Rohan Mclure <rmcl...@linux.ibm.com> > --- > V3 -> V4: New commit. > --- > arch/powerpc/kernel/exceptions-64e.S | 27 +++++++++++--------------- > 1 file changed, 11 insertions(+), 16 deletions(-) > > diff --git a/arch/powerpc/kernel/exceptions-64e.S > b/arch/powerpc/kernel/exceptions-64e.S > index 67dc4e3179a0..48c640ca425d 100644 > --- a/arch/powerpc/kernel/exceptions-64e.S > +++ b/arch/powerpc/kernel/exceptions-64e.S > @@ -216,17 +216,14 @@ END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) > mtlr r10 > mtcr r11 > > - ld r10,GPR10(r1) > - ld r11,GPR11(r1) > - ld r12,GPR12(r1) > + REST_GPRS(10, 12, r1) > mtspr \scratch,r0 > > std r10,\paca_ex+EX_R10(r13); > std r11,\paca_ex+EX_R11(r13); > ld r10,_NIP(r1) > ld r11,_MSR(r1) > - ld r0,GPR0(r1) > - ld r1,GPR1(r1) > + REST_GPRS(0, 1, r1) > mtspr \srr0,r10 > mtspr \srr1,r11 > ld r10,\paca_ex+EX_R10(r13) > @@ -372,16 +369,15 @@ ret_from_mc_except: > /* Core exception code for all exceptions except TLB misses. */ > #define EXCEPTION_COMMON_LVL(n, scratch, excf) > \ > exc_##n##_common: \ > - std r0,GPR0(r1); /* save r0 in stackframe */ \ > - std r2,GPR2(r1); /* save r2 in stackframe */ \ > - SAVE_GPRS(3, 9, r1); /* save r3 - r9 in stackframe */ \ > + SAVE_GPR(0, r1); /* save r0 in stackframe */ \ > + SAVE_GPRS(2, 9, r1); /* save r2 - r9 in stackframe */ \ > std r10,_NIP(r1); /* save SRR0 to stackframe */ \ > std r11,_MSR(r1); /* save SRR1 to stackframe */ \ > beq 2f; /* if from kernel mode */ \ > 2: ld r3,excf+EX_R10(r13); /* get back r10 */ \ > ld r4,excf+EX_R11(r13); /* get back r11 */ \ > mfspr r5,scratch; /* get back r13 */ \ > - std r12,GPR12(r1); /* save r12 in stackframe */ \ > + SAVE_GPR(12, r1); /* save r12 in stackframe */ \ > ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ > mflr r6; /* save LR in stackframe */ \ > mfctr r7; /* save CTR in stackframe */ \ > @@ -390,7 +386,7 @@ exc_##n##_common: > \ > lwz r10,excf+EX_CR(r13); /* load orig CR back from PACA */ \ > lbz r11,PACAIRQSOFTMASK(r13); /* get current IRQ softe */ \ > ld r12,exception_marker@toc(r2); \ > - li r0,0; \ > + ZEROIZE_GPR(0); \ > std r3,GPR10(r1); /* save r10 to stackframe */ \ > std r4,GPR11(r1); /* save r11 to stackframe */ \ > std r5,GPR13(r1); /* save it to stackframe */ \ > @@ -1056,15 +1052,14 @@ bad_stack_book3e: > mfspr r11,SPRN_ESR > std r10,_DEAR(r1) > std r11,_ESR(r1) > - std r0,GPR0(r1); /* save r0 in stackframe */ \ > - std r2,GPR2(r1); /* save r2 in stackframe */ \ > - SAVE_GPRS(3, 9, r1); /* save r3 - r9 in stackframe */ \ > + SAVE_GPR(0, r1); /* save r0 in stackframe */ \ > + SAVE_GPRS(2, 9, r1); /* save r2 - r9 in stackframe */ \ > ld r3,PACA_EXGEN+EX_R10(r13);/* get back r10 */ \ > ld r4,PACA_EXGEN+EX_R11(r13);/* get back r11 */ \ > mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 XXX can be wrong */ \ > std r3,GPR10(r1); /* save r10 to stackframe */ \ > std r4,GPR11(r1); /* save r11 to stackframe */ \ > - std r12,GPR12(r1); /* save r12 in stackframe */ \ > + SAVE_GPR(12, r1); /* save r12 in stackframe */ \ > std r5,GPR13(r1); /* save it to stackframe */ \ > mflr r10 > mfctr r11 > @@ -1072,12 +1067,12 @@ bad_stack_book3e: > std r10,_LINK(r1) > std r11,_CTR(r1) > std r12,_XER(r1) > - SAVE_GPRS(14, 31, r1) > + SAVE_NVGPRS(r1) > lhz r12,PACA_TRAP_SAVE(r13) > std r12,_TRAP(r1) > addi r11,r1,INT_FRAME_SIZE > std r11,0(r1) > - li r12,0 > + ZEROIZE_GPR(12) > std r12,0(r11) > ld r2,PACATOC(r13) > 1: addi r3,r1,STACK_FRAME_OVERHEAD > -- > 2.34.1
