Hi All,
On Wed, Feb 22, 2023 at 11:31:07AM +0530, Kautuk Consul wrote:
> /* The sub-arch has lwsync */
> #if defined(CONFIG_PPC64) || defined(CONFIG_PPC_E500MC)
> -# define SMPWMB LWSYNC
> +#undef rmb
> +#undef wmb
> +/* Redefine rmb() to lwsync. */
> +#define rmb() ({__asm__ __volatile__ ("lwsync" : : : "memory"); })
> +/* Redefine wmb() to lwsync. */
> +#define wmb() ({__asm__ __volatile__ ("lwsync" : : : "memory"); })
> +#define SMPWMB LWSYNC
> #elif defined(CONFIG_BOOKE)
> -# define SMPWMB mbar
> +#define SMPWMB mbar
> #else
> -# define SMPWMB eieio
> +#define SMPWMB eieio
> #endif
I think I am conceptually right about this patch but I lack the
resources currently to tets this out on PowerPC 64 bit servers.
I request IBM/Non-IBM employees to test this patch out for:
a) functionality breaking. This patch is no good if this breaks current
kernel functionality.
b) performance impact. If functionality doesn't break, can anyone do
some reliable kernel load testing on ppc64 servers to see if there
is any significant performance gain ?
Thanks a lot!
