[PATCH] ASoC: fsl_xcvr: refine the requested phy clock frequency

[Shengjiu Wang]

As the input phy clock frequency will divided by 2 by default
on i.MX8MP with the implementation of clk-imx8mp-audiomix driver,
So the requested frequency need to be updated.

The relation of phy clock is:
    sai_pll_ref_sel
       sai_pll
          sai_pll_bypass
             sai_pll_out
                sai_pll_out_div2
                   earc_phy_cg

Signed-off-by: Shengjiu Wang <shengjiu.w...@nxp.com>
---
 sound/soc/fsl/fsl_xcvr.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/sound/soc/fsl/fsl_xcvr.c b/sound/soc/fsl/fsl_xcvr.c
index 77f8e2394bf9..f0fb33d719c2 100644
--- a/sound/soc/fsl/fsl_xcvr.c
+++ b/sound/soc/fsl/fsl_xcvr.c
@@ -358,7 +358,7 @@ static int fsl_xcvr_en_aud_pll(struct fsl_xcvr *xcvr, u32 
freq)
        struct device *dev = &xcvr->pdev->dev;
        int ret;
 
-       freq = xcvr->soc_data->spdif_only ? freq / 10 : freq;
+       freq = xcvr->soc_data->spdif_only ? freq / 5 : freq;
        clk_disable_unprepare(xcvr->phy_clk);
        ret = clk_set_rate(xcvr->phy_clk, freq);
        if (ret < 0) {
@@ -409,7 +409,7 @@ static int fsl_xcvr_prepare(struct snd_pcm_substream 
*substream,
        bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
        u32 m_ctl = 0, v_ctl = 0;
        u32 r = substream->runtime->rate, ch = substream->runtime->channels;
-       u32 fout = 32 * r * ch * 10 * 2;
+       u32 fout = 32 * r * ch * 10;
        int ret = 0;
 
        switch (xcvr->mode) {
-- 
2.34.1