> On 29-Nov-2023, at 10:51 AM, Athira Rajeev <atraj...@linux.vnet.ibm.com>
> wrote:
>
>
>
>> On 27-Nov-2023, at 5:32 PM, Disha Goel <disg...@linux.ibm.com> wrote:
>>
>> On 23/11/23 9:31 pm, Athira Rajeev wrote:
>>
>>> Running "perf list" on powerpc fails with segfault
>>> as below:
>>>
>>> ./perf list
>>> Segmentation fault (core dumped)
>>>
>>> This happens because of duplicate events in the json list.
>>> The powerpc Json event list contains some event with same
>>> event name, but different event code. They are:
>>> - PM_INST_FROM_L3MISS (Present in datasource and frontend)
>>> - PM_MRK_DATA_FROM_L2MISS (Present in datasource and marked)
>>> - PM_MRK_INST_FROM_L3MISS (Present in datasource and marked)
>>> - PM_MRK_DATA_FROM_L3MISS (Present in datasource and marked)
>>>
>>> pmu_events_table__num_events uses the value from
>>> table_pmu->num_entries which includes duplicate events as
>>> well. This causes issue during "perf list" and results in
>>> segmentation fault.
>>>
>>> Since both event codes are valid, append _DSRC to the Data
>>> Source events (datasource.json), so that they would have a
>>> unique name. Also add PM_DATA_FROM_L2MISS_DSRC and
>>> PM_DATA_FROM_L3MISS_DSRC events. With the fix, perf list
>>> works as expected.
>>>
>>> Fixes: fc1435807533 ("perf vendor events power10: Update JSON/events")
>>> Signed-off-by: Athira Rajeev <atraj...@linux.vnet.ibm.com>
>>
>> I have tested the patch on Power10 machine. Perf list works correctly
>> without any segfault now.
>>
>> # ./perf list
>>
>> List of pre-defined events (to be used in -e or -M):
>>
>> branch-instructions OR branches [Hardware event]
>> branch-misses [Hardware event]
>>
>> Tested-by: Disha Goel <disg...@linux.ibm.com>
>>
>
> Thanks Disha for testing
>
> Athira
Hi Arnaldo,
Can we get this pulled in if the patch looks good ?
Thanks
Athira
>>> ---
>>> .../arch/powerpc/power10/datasource.json | 18 ++++++++++++++----
>>> 1 file changed, 14 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/tools/perf/pmu-events/arch/powerpc/power10/datasource.json
>>> b/tools/perf/pmu-events/arch/powerpc/power10/datasource.json
>>> index 6b0356f2d301..0eeaaf1a95b8 100644
>>> --- a/tools/perf/pmu-events/arch/powerpc/power10/datasource.json
>>> +++ b/tools/perf/pmu-events/arch/powerpc/power10/datasource.json
>>> @@ -99,6 +99,11 @@
>>> "EventName": "PM_INST_FROM_L2MISS",
>>> "BriefDescription": "The processor's instruction cache was reloaded
>>> from a source beyond the local core's L2 due to a demand miss."
>>> },
>>> + {
>>> + "EventCode": "0x0003C0000000C040",
>>> + "EventName": "PM_DATA_FROM_L2MISS_DSRC",
>>> + "BriefDescription": "The processor's L1 data cache was reloaded from a
>>> source beyond the local core's L2 due to a demand miss."
>>> + },
>>> {
>>> "EventCode": "0x000380000010C040",
>>> "EventName": "PM_INST_FROM_L2MISS_ALL",
>>> @@ -161,9 +166,14 @@
>>> },
>>> {
>>> "EventCode": "0x000780000000C040",
>>> - "EventName": "PM_INST_FROM_L3MISS",
>>> + "EventName": "PM_INST_FROM_L3MISS_DSRC",
>>> "BriefDescription": "The processor's instruction cache was reloaded
>>> from beyond the local core's L3 due to a demand miss."
>>> },
>>> + {
>>> + "EventCode": "0x0007C0000000C040",
>>> + "EventName": "PM_DATA_FROM_L3MISS_DSRC",
>>> + "BriefDescription": "The processor's L1 data cache was reloaded from
>>> beyond the local core's L3 due to a demand miss."
>>> + },
>>> {
>>> "EventCode": "0x000780000010C040",
>>> "EventName": "PM_INST_FROM_L3MISS_ALL",
>>> @@ -981,7 +991,7 @@
>>> },
>>> {
>>> "EventCode": "0x0003C0000000C142",
>>> - "EventName": "PM_MRK_DATA_FROM_L2MISS",
>>> + "EventName": "PM_MRK_DATA_FROM_L2MISS_DSRC",
>>> "BriefDescription": "The processor's L1 data cache was reloaded from a
>>> source beyond the local core's L2 due to a demand miss for a marked
>>> instruction."
>>> },
>>> {
>>> @@ -1046,12 +1056,12 @@
>>> },
>>> {
>>> "EventCode": "0x000780000000C142",
>>> - "EventName": "PM_MRK_INST_FROM_L3MISS",
>>> + "EventName": "PM_MRK_INST_FROM_L3MISS_DSRC",
>>> "BriefDescription": "The processor's instruction cache was reloaded
>>> from beyond the local core's L3 due to a demand miss for a marked
>>> instruction."
>>> },
>>> {
>>> "EventCode": "0x0007C0000000C142",
>>> - "EventName": "PM_MRK_DATA_FROM_L3MISS",
>>> + "EventName": "PM_MRK_DATA_FROM_L3MISS_DSRC",
>>> "BriefDescription": "The processor's L1 data cache was reloaded from
>>> beyond the local core's L3 due to a demand miss for a marked instruction."
>>> },
>>> {
