On Wed, Jul 30, 2025 at 11:28:18AM -0300, Jason Gunthorpe wrote: > On Wed, Jul 30, 2025 at 04:40:26PM +0300, Leon Romanovsky wrote:
<...> > > The most reasonable way to prevent DMA_ATTR_SKIP_CPU_SYNC leakage is to > > introduce new DMA attribute (let's call it DMA_ATTR_MMIO for now) and > > pass it to both dma_map_phys() and dma_iova_link(). This flag will > > indicate that p2p type is PCI_P2PDMA_MAP_THRU_HOST_BRIDGE and call to > > right callbacks which will set IOMMU_MMIO flag and skip CPU sync, > > So the idea is if the memory is non-cachable, no-KVA you'd call > dma_iova_link(phys_addr, DMA_ATTR_MMIO) and dma_map_phys(phys_addr, > DMA_ATTR_MMIO) ? Yes > > And then internally the dma_ops and dma_iommu would use the existing > map_page/map_resource variations based on the flag, thus ensuring that > MMIO is never kmap'd or cache flushed? > > dma_map_resource is really then just > dma_map_phys(phys_addr, DMA_ATTR_MMIO)? > > I like this, I think it well addresses the concerns. Yes, I had this idea and implementation before. :( > > Jason >
