On Thu, Aug 07, 2025 at 04:44:30PM -0500, Rob Herring (Arm) wrote: > The chrp,open-pic binding schema already supports the "fsl,mpic" > compatible. A couple of properties are missing, so add them and remove > fsl/mpic.txt. > > Signed-off-by: Rob Herring (Arm) <r...@kernel.org>
What about the 4-cell interrupt specifiers? > - 0 = external or normal SoC device interrupt > - > - The interrupt-number cell contains > - the SoC device interrupt number. The > - type-specific cell is undefined. The > - interrupt-number is derived from the > - MPIC a block of registers referred to as > - the "Interrupt Source Configuration Registers". > - Each source has 32-bytes of registers > - (vector/priority and destination) in this > - region. So interrupt 0 is at offset 0x0, > - interrupt 1 is at offset 0x20, and so on. FWIW, while this description may seem unnecessarily verbose, it's because it's different from how Freescale hardware docs numbered the IRQs (IRQ 16 was "internal IRQ 0", etc). -Crystal
