The QUICC Engine provides interrupts for a few I/O ports. This is
handled via a separate interrupt ID and managed via a triplet of
dedicated registers hosted by the SoC.
Implement an interrupt driver for those IRQs then add IRQs capability to
the QUICC ENGINE GPIOs.
The number of GPIOs for which interrupts are supported depends on
the microcontroller:
- mpc8323 has 10 GPIOS supporting interrupts
- mpc8360 has 28 GPIOS supporting interrupts
- mpc8568 has 18 GPIOS supporting interrupts
Christophe Leroy (4):
soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports
soc: fsl: qe: Change GPIO driver to a proper platform driver
soc: fsl: qe: Add support of IRQ in QE GPIO
dt-bindings: soc: fsl: qe: Add an interrupt controller for QUICC
Engine Ports
.../soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml | 63 +++++++
drivers/soc/fsl/qe/Makefile | 2 +-
drivers/soc/fsl/qe/gpio.c | 108 ++++++++----
drivers/soc/fsl/qe/qe_ports_ic.c | 156 ++++++++++++++++++
4 files changed, 293 insertions(+), 36 deletions(-)
create mode 100644
Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml
create mode 100644 drivers/soc/fsl/qe/qe_ports_ic.c
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2.49.0
