In the QE, a few GPIOs are IRQ capable. Similarly to
commit 726bd223105c ("powerpc/8xx: Adding support of IRQ in MPC8xx
GPIO"), add IRQ support to QE GPIO.

Add property 'fsl,qe-gpio-irq-mask' similar to
'fsl,cpm1-gpio-irq-mask' that define which of the GPIOs have IRQs.

Here is an exemple for port B of mpc8323 which has IRQs for
GPIOs PB7, PB9, PB25 and PB27.

        qe_pio_b: gpio-controller@1418 {
                #gpio-cells = <2>;
                compatible = "fsl,mpc8323-qe-pario-bank";
                reg = <0x1418 0x18>;
                interrupts = <4 5 6 7>;
                fsl,qe-gpio-irq-mask = <0x01400050>;
                interrupt-parent = <&qepic>;
                gpio-controller;
        };

Signed-off-by: Christophe Leroy <christophe.le...@csgroup.eu>
---
v2: Document fsl,qe-gpio-irq-mask
---
 .../bindings/soc/fsl/cpm_qe/qe/par_io.txt     | 19 ++++++++++++++++++
 drivers/soc/fsl/qe/gpio.c                     | 20 +++++++++++++++++++
 2 files changed, 39 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt 
b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt
index 09b1b05fa677..9cd6e5ac2a7b 100644
--- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt
+++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt
@@ -32,6 +32,15 @@ Required properties:
   "fsl,mpc8323-qe-pario-bank".
 - reg : offset to the register set and its length.
 - gpio-controller : node to identify gpio controllers.
+Optional properties:
+- fsl,qe-gpio-irq-mask : For banks having interrupt capability this item tells
+  which ports have an associated interrupt (ports are listed in the same order
+  QE ports registers)
+- interrupts : This property provides the list of interrupt for each GPIO 
having
+  one as described by the fsl,cpm1-gpio-irq-mask property. There should be as
+  many interrupts as number of ones in the mask property. The first interrupt 
in
+  the list corresponds to the most significant bit of the mask.
+- interrupt-parent : Parent for the above interrupt property.
 
 Example:
        qe_pio_a: gpio-controller@1400 {
@@ -42,6 +51,16 @@ Example:
                gpio-controller;
          };
 
+       qe_pio_b: gpio-controller@1418 {
+               #gpio-cells = <2>;
+               compatible = "fsl,mpc8323-qe-pario-bank";
+               reg = <0x1418 0x18>;
+               interrupts = <4 5 6 7>;
+               fsl,qe-gpio-irq-mask = <0x01400050>;
+               interrupt-parent = <&qepic>;
+               gpio-controller;
+         };
+
        qe_pio_e: gpio-controller@1460 {
                #gpio-cells = <2>;
                compatible = "fsl,mpc8360-qe-pario-bank",
diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c
index a338469cebe4..91d469403126 100644
--- a/drivers/soc/fsl/qe/gpio.c
+++ b/drivers/soc/fsl/qe/gpio.c
@@ -13,6 +13,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/of.h>
+#include <linux/of_irq.h>
 #include <linux/gpio/consumer.h>
 #include <linux/gpio/driver.h>
 #include <linux/slab.h>
@@ -32,6 +33,8 @@ struct qe_gpio_chip {
 
        /* saved_regs used to restore dedicated functions */
        struct qe_pio_regs saved_regs;
+
+       int irq[32];
 };
 
 static void qe_gpio_save_regs(struct qe_gpio_chip *qe_gc)
@@ -135,6 +138,13 @@ static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned 
int gpio, int val)
        return 0;
 }
 
+static int qe_gpio_to_irq(struct gpio_chip *gc, unsigned int gpio)
+{
+       struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
+
+       return qe_gc->irq[gpio] ? : -ENXIO;
+}
+
 struct qe_pin {
        /*
         * The qe_gpio_chip name is unfortunate, we should change that to
@@ -295,6 +305,7 @@ static int qe_gpio_probe(struct platform_device *ofdev)
        struct device_node *np = dev->of_node;
        struct qe_gpio_chip *qe_gc;
        struct gpio_chip *gc;
+       u32 mask;
 
        qe_gc = devm_kzalloc(dev, sizeof(*qe_gc), GFP_KERNEL);
        if (!qe_gc)
@@ -302,6 +313,14 @@ static int qe_gpio_probe(struct platform_device *ofdev)
 
        spin_lock_init(&qe_gc->lock);
 
+       if (!of_property_read_u32(np, "fsl,qe-gpio-irq-mask", &mask)) {
+               int i, j;
+
+               for (i = 0, j = 0; i < ARRAY_SIZE(qe_gc->irq); i++)
+                       if (mask & (1 << (31 - i)))
+                               qe_gc->irq[i] = irq_of_parse_and_map(np, j++);
+       }
+
        gc = &qe_gc->gc;
 
        gc->base = -1;
@@ -311,6 +330,7 @@ static int qe_gpio_probe(struct platform_device *ofdev)
        gc->get = qe_gpio_get;
        gc->set = qe_gpio_set;
        gc->set_multiple = qe_gpio_set_multiple;
+       gc->to_irq = qe_gpio_to_irq;
        gc->parent = dev;
        gc->owner = THIS_MODULE;
 
-- 
2.49.0


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