On Mon, 2025-09-15 at 15:50 +0200, Lukas Wunner wrote:
> Commit 11502feab423 ("Documentation: PCI: Tidy AER documentation")
> replaced the terms "PCI-E", "PCI-Express" and "PCI Express" with "PCIe"
> in the AER documentation.
>
> Do the same in the documentation on PCI error recovery. While at it,
> add a missing period and a missing blank.
>
> Signed-off-by: Lukas Wunner <lu...@wunner.de>
> Reviewed-by: Brian Norris <briannor...@chromium.org>
> ---
> Documentation/PCI/pci-error-recovery.rst | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/Documentation/PCI/pci-error-recovery.rst
> b/Documentation/PCI/pci-error-recovery.rst
> index 9e1e2f2a13fa..5df481ac6193 100644
> --- a/Documentation/PCI/pci-error-recovery.rst
> +++ b/Documentation/PCI/pci-error-recovery.rst
> @@ -13,7 +13,7 @@ PCI Error Recovery
> Many PCI bus controllers are able to detect a variety of hardware
> PCI errors on the bus, such as parity errors on the data and address
> buses, as well as SERR and PERR errors. Some of the more advanced
> -chipsets are able to deal with these errors; these include PCI-E chipsets,
> +chipsets are able to deal with these errors; these include PCIe chipsets,
> and the PCI-host bridges found on IBM Power4, Power5 and Power6-based
> pSeries boxes. A typical action taken is to disconnect the affected device,
> halting all I/O to it. The goal of a disconnection is to avoid system
> @@ -206,7 +206,7 @@ reset or some such, but not restart operations. This
> callback is made if
> all drivers on a segment agree that they can try to recover and if no
> automatic
> link reset was performed by the HW. If the platform can't just re-enable IOs
> without a slot reset or a link reset, it will not call this callback, and
> -instead will have gone directly to STEP 3 (Link Reset) or STEP 4 (Slot Reset)
> +instead will have gone directly to STEP 3 (Link Reset) or STEP 4 (Slot
> Reset).
>
> .. note::
>
> @@ -259,14 +259,14 @@ The driver should return one of the following result
> codes:
>
> The next step taken depends on the results returned by the drivers.
> If all drivers returned PCI_ERS_RESULT_RECOVERED, then the platform
> -proceeds to either STEP3 (Link Reset) or to STEP 5 (Resume Operations).
> +proceeds to either STEP 3 (Link Reset) or to STEP 5 (Resume Operations).
>
> If any driver returned PCI_ERS_RESULT_NEED_RESET, then the platform
> proceeds to STEP 4 (Slot Reset)
>
> STEP 3: Link Reset
> ------------------
> -The platform resets the link. This is a PCI-Express specific step
> +The platform resets the link. This is a PCIe specific step
> and is done whenever a fatal error has been detected that can be
> "solved" by resetting the link.
>
> @@ -288,13 +288,13 @@ that is equivalent to what it would be after a fresh
> system
> power-on followed by power-on BIOS/system firmware initialization.
> Soft reset is also known as hot-reset.
>
> -Powerpc fundamental reset is supported by PCI Express cards only
> +Powerpc fundamental reset is supported by PCIe cards only
> and results in device's state machines, hardware logic, port states and
> configuration registers to initialize to their default conditions.
>
> For most PCI devices, a soft reset will be sufficient for recovery.
> Optional fundamental reset is provided to support a limited number
> -of PCI Express devices for which a soft reset is not sufficient
> +of PCIe devices for which a soft reset is not sufficient
> for recovery.
>
> If the platform supports PCI hotplug, then the reset might be
> @@ -338,7 +338,7 @@ Result codes:
> - PCI_ERS_RESULT_DISCONNECT
> Same as above.
>
> -Drivers for PCI Express cards that require a fundamental reset must
> +Drivers for PCIe cards that require a fundamental reset must
> set the needs_freset bit in the pci_dev structure in their probe function.
> For example, the QLogic qla2xxx driver sets the needs_freset bit for certain
> PCI card types::
Thanks for the bringing this in sync.
Reviewed-by: Niklas Schnelle <schne...@linux.ibm.com>
