From: Alexander Stein <[email protected]> [ Upstream commit 90ed688792a6b7012b3e8a2f858bc3fe7454d0eb ]
Drivers does cache sync during runtime resume, setting all writable registers. Not all writable registers are set in cache default, resulting in the erorr message: fsl-sai 30c30000.sai: using zero-initialized flat cache, this may cause unexpected behavior Fix this by adding missing writable register defaults. Signed-off-by: Alexander Stein <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Mark Brown <[email protected]> Signed-off-by: Sasha Levin <[email protected]> --- LLM Generated explanations, may be completely bogus: ## Analysis Summary ### 1. What Problem Does This Commit Solve? This commit fixes a bug where the FSL SAI driver's regmap cache was incomplete. During runtime resume, the driver performs a cache sync that writes all writable registers. Two writable registers (`FSL_SAI_TTCTL` and `FSL_SAI_RTCTL`) were missing from the cache defaults array, causing: 1. A warning message: `fsl-sai 30c30000.sai: using zero-initialized flat cache, this may cause unexpected behavior` 2. Potentially incorrect behavior during suspend/resume cycles ### 2. Root Cause Analysis The bug was introduced in commit `0b2cbce68986` ("ASoC: fsl_sai: Add new added registers and new bit definition") from September 2020, which: - Added `FSL_SAI_TTCTL` and `FSL_SAI_RTCTL` to `fsl_sai_writeable_reg()` (lines 1234-1235) - But **failed** to add them to `fsl_sai_reg_defaults_ofs0[]` and `fsl_sai_reg_defaults_ofs8[]` The current commit completes what should have been done in the original commit. ### 3. Code Change Assessment The fix is minimal and surgical: - Adds `{FSL_SAI_TTCTL, 0}` to `fsl_sai_reg_defaults_ofs0[]` (+1 line) - Adds `{FSL_SAI_TTCTL, 0}` to `fsl_sai_reg_defaults_ofs8[]` (+1 line) - Adds `{FSL_SAI_RTCTL, 0}` to `fsl_sai_reg_defaults_ofs8[]` (+1 line) Total: 3 lines added, all initializing registers to default value 0. ### 4. Stable Criteria Check | Criteria | Assessment | |----------|------------| | Obviously correct | ✅ Yes - completing missing register defaults | | Fixes real bug | ✅ Yes - fixes warning and potential misbehavior | | Small scope | ✅ Yes - only 3 lines added to static arrays | | No new features | ✅ Yes - purely fixes incomplete initialization | | Tested | ✅ Accepted by subsystem maintainer (Mark Brown) | ### 5. Risk Assessment **Risk: Very Low** - No logic changes, only adds entries to static const arrays - Default values are 0 (standard hardware reset value) - The registers already existed and were marked writable - Change is purely additive to existing data structures ### 6. Affected Stable Trees The bug exists in kernels v5.10+ (when commit 0b2cbce68986 was merged). Relevant stable trees: - 5.10.y (LTS) - 5.15.y (LTS) - 6.1.y (LTS) - 6.6.y (LTS) - 6.11.y and newer ### 7. User Impact Affects users of NXP/Freescale i.MX processors using SAI audio interfaces, particularly those using suspend/resume (common on embedded systems, tablets, etc.). ### Conclusion This is an excellent stable backport candidate. It's a minimal, low-risk fix that corrects a longstanding bug in driver initialization. The fix simply completes the register cache defaults that should have been included when the registers were made writable in 2020. The warning message indicates potential undefined behavior, and the fix is as simple and safe as adding entries to a static array. **YES** sound/soc/fsl/fsl_sai.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index 72bfc91e21b9..090354a0f711 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -1075,6 +1075,7 @@ static const struct reg_default fsl_sai_reg_defaults_ofs0[] = { {FSL_SAI_TDR6, 0}, {FSL_SAI_TDR7, 0}, {FSL_SAI_TMR, 0}, + {FSL_SAI_TTCTL, 0}, {FSL_SAI_RCR1(0), 0}, {FSL_SAI_RCR2(0), 0}, {FSL_SAI_RCR3(0), 0}, @@ -1098,12 +1099,14 @@ static const struct reg_default fsl_sai_reg_defaults_ofs8[] = { {FSL_SAI_TDR6, 0}, {FSL_SAI_TDR7, 0}, {FSL_SAI_TMR, 0}, + {FSL_SAI_TTCTL, 0}, {FSL_SAI_RCR1(8), 0}, {FSL_SAI_RCR2(8), 0}, {FSL_SAI_RCR3(8), 0}, {FSL_SAI_RCR4(8), 0}, {FSL_SAI_RCR5(8), 0}, {FSL_SAI_RMR, 0}, + {FSL_SAI_RTCTL, 0}, {FSL_SAI_MCTL, 0}, {FSL_SAI_MDIV, 0}, }; -- 2.51.0
