The QUICC Engine provides interrupts for a few I/O ports. This is handled via a separate interrupt ID and managed via a triplet of dedicated registers hosted by the SoC.
Implement an interrupt driver for it so that those IRQs can then be linked to the related GPIOs. Signed-off-by: Christophe Leroy (CS GROUP) <[email protected]> Acked-by: Conor Dooley <[email protected]> --- .../soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml new file mode 100644 index 0000000000000..1f3c652b1569d --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale QUICC Engine I/O Ports Interrupt Controller + +maintainers: + - Christophe Leroy (CS GROUP) <[email protected]> + +properties: + compatible: + enum: + - fsl,mpc8323-qe-ports-ic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#address-cells': + const: 0 + + '#interrupt-cells': + const: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupt-controller + - '#address-cells' + - '#interrupt-cells' + - interrupts + +additionalProperties: false + +examples: + - | + interrupt-controller@c00 { + compatible = "fsl,mpc8323-qe-ports-ic"; + reg = <0xc00 0x18>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupts = <74 0x8>; + interrupt-parent = <&ipic>; + }; -- 2.49.0
