On 1/27/26 6:45 PM, Jonathan Cameron wrote:
On Sat, 24 Jan 2026 15:45:57 +0800
Shuai Xue <[email protected]> wrote:
Currently, pcie_clear_device_status() clears the entire PCIe Device
Status register (PCI_EXP_DEVSTA), which includes both error status bits
and other status bits such as AUX Power Detected (AUXPD) and
Transactions Pending (TRPND).
Clearing non-error status bits can interfere with other drivers or
subsystems that may rely on these bits. To fix it, only clear the error
bits (0xf) while preserving other status bits.
Fixes: ec752f5d54d7 ("PCI/AER: Clear device status bits during ERR_FATAL and
ERR_NONFATAL")
Cc: [email protected]
Suggested-by: Lukas Wunner <[email protected]>
Signed-off-by: Shuai Xue <[email protected]>
Similar to previous. Drag to start of series to make backports easier if
we think this is a fix that affects real cases.
Thank you for the detailed feedback.
I'll move this patch to the start of the series for easier backporting.
For stuff that's defined
in the PCI 6.2 spec, AUX power and Transactions Pending are RO, but
the interesting one is Emergency Power Reduction Detected which is RW1C
and hence reason this fix is potentially needed + future features using
remaining bits.
I'd be more explicit in the commit message for that. Talk about it not
mattering for AUXPD or TRPND because they are RO, vs the ones we
aren't using yet in Linux with the emergency power reduction detected
as an example that clearly shows we need to mask this!
You're absolutely right - the commit
message should be more explicit about the different bit types and their
implications.
The revised the commit message is:
PCI/AER: Only clear error bits in PCIe Device Status register
Currently, pcie_clear_device_status() clears the entire PCIe Device
Status register (PCI_EXP_DEVSTA), which includes both error status bits
and other status bits.
According to PCIe Base Spec r6.0 sec 7.5.3.5, the Device Status register
contains different types of status bits:
- Read-only bits (AUXPD, TRPND): Writing to these has no effect, but
clearing them is unnecessary.
- RW1C (read/write 1 to clear) non-error bits: For example, Emergency
Power Reduction Detected (bit 6). Unconditionally clearing these bits
can interfere with other drivers or subsystems that rely on them.
- Reserved bits: May be used for future features and should be preserved.
To prevent unintended side effects, modify pcie_clear_device_status() to
only clear the four error status bits (CED, NFED, FED, URD) while
preserving all other status bits.
Fixes: ec752f5d54d7 ("PCI/AER: Clear device status bits during ERR_FATAL and
ERR_NONFATAL")
Cc: [email protected]
Suggested-by: Lukas Wunner <[email protected]>
Signed-off-by: Shuai Xue <[email protected]>
J
Thanks.
Best Regards,
Shuai
