The transmitter and receiver implement separate timestamp counters and bit counters. The bit counter increments at the end of each bit in a frame whenever the transmitter or receiver is enabled. The bit counter can be reset by software. The timestamp counter increments on the bus interface clock whenever it is enabled. The current value of the timestamp counter is latched whenever the bit counter increments. Reading the bit counter register will cause the latched timestamp value to be saved in the bit counter timestamp register. The timestamp counter can be reset by software, this also resets the latched timestamp value and the bit counter timestamp register.
The timestamp counter and bit counter can be used by software to track the progress of the transmitter and receiver. It can also be used to calculate the relative frequency of the bit clock against the bus interface clock. As there are three regmap handlers defined in this driver, explicitly call the snd_soc_component_init_regmap() to init regmap handler for the component. Signed-off-by: Shengjiu Wang <[email protected]> --- sound/soc/fsl/fsl_xcvr.c | 56 ++++++++++++++++++++++++++++++++++++++++ sound/soc/fsl/fsl_xcvr.h | 10 +++++++ 2 files changed, 66 insertions(+) diff --git a/sound/soc/fsl/fsl_xcvr.c b/sound/soc/fsl/fsl_xcvr.c index 5de93f458b56..d9e76ea9cf07 100644 --- a/sound/soc/fsl/fsl_xcvr.c +++ b/sound/soc/fsl/fsl_xcvr.c @@ -62,6 +62,50 @@ struct fsl_xcvr { u32 spdif_constr_rates_list[SPDIF_NUM_RATES]; }; +static const char * const inc_mode[] = { + "On enabled and bitcount increment", "On enabled" +}; + +static const struct soc_enum tstmp_enum[] = { + SOC_ENUM_SINGLE(FSL_XCVR_TX_DPTH_CNTR_CTRL, __bf_shf(FSL_XCVR_TX_DPTH_CNTR_CTRL_TSINC), + ARRAY_SIZE(inc_mode), inc_mode), + SOC_ENUM_SINGLE(FSL_XCVR_RX_DPTH_CNTR_CTRL, __bf_shf(FSL_XCVR_RX_DPTH_CNTR_CTRL_TSINC), + ARRAY_SIZE(inc_mode), inc_mode), +}; + +static const struct snd_kcontrol_new fsl_xcvr_timestamp_ctrls[] = { + SOC_SINGLE("Transmit Timestamp Control Switch", FSL_XCVR_TX_DPTH_CNTR_CTRL, + __bf_shf(FSL_XCVR_TX_DPTH_CNTR_CTRL_TSEN), 1, 0), + SOC_ENUM("Transmit Timestamp Increment", tstmp_enum[0]), + SOC_SINGLE("Transmit Timestamp Reset", FSL_XCVR_TX_DPTH_CNTR_CTRL, + __bf_shf(FSL_XCVR_TX_DPTH_CNTR_CTRL_RTSC), 1, 0), + SOC_SINGLE("Transmit Bit Counter Reset", FSL_XCVR_TX_DPTH_CNTR_CTRL, + __bf_shf(FSL_XCVR_TX_DPTH_CNTR_CTRL_RBC), 1, 0), + SOC_SINGLE_XR_SX("Transmit Timestamp Counter", FSL_XCVR_TX_DPTH_TSCR, + 1, 32, 0, 0xffffffff, 0), + SOC_SINGLE_XR_SX("Transmit Bit Counter", FSL_XCVR_TX_DPTH_BCR, + 1, 32, 0, 0xffffffff, 0), + SOC_SINGLE_XR_SX("Transmit Bit Count Timestamp", FSL_XCVR_TX_DPTH_BCTR, + 1, 32, 0, 0xffffffff, 0), + SOC_SINGLE_XR_SX("Transmit Latched Timestamp Counter", FSL_XCVR_TX_DPTH_BCRR, + 1, 32, 0, 0xffffffff, 0), + SOC_SINGLE("Receive Timestamp Control Switch", FSL_XCVR_RX_DPTH_CNTR_CTRL, + __bf_shf(FSL_XCVR_RX_DPTH_CNTR_CTRL_TSEN), 1, 0), + SOC_ENUM("Receive Timestamp Increment", tstmp_enum[1]), + SOC_SINGLE("Receive Timestamp Reset", FSL_XCVR_RX_DPTH_CNTR_CTRL, + __bf_shf(FSL_XCVR_RX_DPTH_CNTR_CTRL_RTSC), 1, 0), + SOC_SINGLE("Receive Bit Counter Reset", FSL_XCVR_RX_DPTH_CNTR_CTRL, + __bf_shf(FSL_XCVR_RX_DPTH_CNTR_CTRL_RBC), 1, 0), + SOC_SINGLE_XR_SX("Receive Timestamp Counter", FSL_XCVR_RX_DPTH_TSCR, + 1, 32, 0, 0xffffffff, 0), + SOC_SINGLE_XR_SX("Receive Bit Counter", FSL_XCVR_RX_DPTH_BCR, + 1, 32, 0, 0xffffffff, 0), + SOC_SINGLE_XR_SX("Receive Bit Count Timestamp", FSL_XCVR_RX_DPTH_BCTR, + 1, 32, 0, 0xffffffff, 0), + SOC_SINGLE_XR_SX("Receive Latched Timestamp Counter", FSL_XCVR_RX_DPTH_BCRR, + 1, 32, 0, 0xffffffff, 0), +}; + static const struct fsl_xcvr_pll_conf { u8 mfi; /* min=0x18, max=0x38 */ u32 mfn; /* signed int, 2's compl., min=0x3FFF0000, max=0x00010000 */ @@ -1073,8 +1117,20 @@ static struct snd_soc_dai_driver fsl_xcvr_dai = { }, }; +static int fsl_xcvr_component_probe(struct snd_soc_component *component) +{ + struct fsl_xcvr *xcvr = snd_soc_component_get_drvdata(component); + + snd_soc_component_init_regmap(component, xcvr->regmap); + + return 0; +} + static const struct snd_soc_component_driver fsl_xcvr_comp = { .name = "fsl-xcvr-dai", + .probe = fsl_xcvr_component_probe, + .controls = fsl_xcvr_timestamp_ctrls, + .num_controls = ARRAY_SIZE(fsl_xcvr_timestamp_ctrls), .legacy_dai_naming = 1, }; diff --git a/sound/soc/fsl/fsl_xcvr.h b/sound/soc/fsl/fsl_xcvr.h index dade3945cc0c..1c3636567763 100644 --- a/sound/soc/fsl/fsl_xcvr.h +++ b/sound/soc/fsl/fsl_xcvr.h @@ -233,6 +233,16 @@ #define FSL_XCVR_TX_DPTH_CTRL_CLK_RATIO BIT(29) #define FSL_XCVR_TX_DPTH_CTRL_TM_NO_PRE_BME GENMASK(31, 30) +#define FSL_XCVR_RX_DPTH_CNTR_CTRL_TSEN BIT(0) +#define FSL_XCVR_RX_DPTH_CNTR_CTRL_TSINC BIT(1) +#define FSL_XCVR_RX_DPTH_CNTR_CTRL_RBC BIT(8) +#define FSL_XCVR_RX_DPTH_CNTR_CTRL_RTSC BIT(9) + +#define FSL_XCVR_TX_DPTH_CNTR_CTRL_TSEN BIT(0) +#define FSL_XCVR_TX_DPTH_CNTR_CTRL_TSINC BIT(1) +#define FSL_XCVR_TX_DPTH_CNTR_CTRL_RBC BIT(8) +#define FSL_XCVR_TX_DPTH_CNTR_CTRL_RTSC BIT(9) + #define FSL_XCVR_PHY_AI_CTRL_AI_RESETN BIT(15) #define FSL_XCVR_PHY_AI_CTRL_AI_RWB BIT(31) -- 2.34.1
