On Mon, Oct 13, 2008 at 11:20:20AM -0500, Scott Wood wrote:
> On Mon, Oct 13, 2008 at 11:15:47AM -0500, Scott Wood wrote:
> > On Sun, Oct 12, 2008 at 07:47:32AM +0200, Nick Piggin wrote:
> > > +static inline int __mutex_cmpxchg_lock(atomic_t *v, int old, int new)
> > > +{
> > > + int t;
> > > +
> > > + __asm__ __volatile__ (
> > > +"1: lwarx %0,0,%1 # mutex trylock\n\
> > > + cmpw 0,%0,%2\n\
> > > + bne- 2f\n"
> > > + PPC405_ERR77(0,%1)
> > > +" stwcx. %3,0,%1\n\
> > > + bne- 1b"
> > > + ISYNC_ON_SMP
> > > + "\n\
> > > +2:"
> > > + : "=&r" (t)
> > > + : "r" (&v->counter), "r" (old), "r" (new)
> > > + : "cc", "memory");
> >
> > This will break if the compiler picks r0 for &v->counter. Use "b" as the
> > constraint, or better yet do "lwarx %0, %y1", with a "Z" (v->counter)
> > constraint.
>
> Sorry, had a morning brain-fart there -- you're not using the base
> register.
OK no problem. Do you think it looks OK? Thanks for reviewing...
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