On Wed, Jul 08, 2026 at 12:15:17PM +0200, Paul Louvel wrote: > Some QE GPIO pins have an associated interrupt line in the QE PIC to > signal state changes on the pin. Add the corresponding > interrupt-controller / nexus properties to the QE GPIO binding. > > Because the GPIO controller does not perform any interrupt handling > itself, a nexus node (interrupt-map) is used to map each GPIO line > supporting IRQ to the parent QE PIC interrupt domain. > > As the QE PIC can be configured to generate an interrupt on either a > high-to-low transition or any change in signal state, three > interrupt-map entries are needed per GPIO pin that can yield an > interrupt (falling, both, and the "none" case which defaults to both in > QE PIC). This overhead is necessary because the interrupt-map-pass-thru > property is not part of the DT specification. > > The interrupt-map property is optional: it is not required for GPIO > banks that have no interrupt capable GPIO line (e.g. port D on MPC8323), > or when interrupt functionality is not used. > > Update the example to show a scenario where each bank supports a > different numbers of IRQs, or no IRQs at all. > > Signed-off-by: Paul Louvel <[email protected]> > --- > .../bindings/gpio/fsl,mpc8323-qe-pario-bank.yaml | 39 > ++++++++++++++++++++++ > 1 file changed, 39 insertions(+)
Reviewed-by: Krzysztof Kozlowski <[email protected]> Best regards, Krzysztof
