Re: [PATCH net v3] net: dpaa: fix mode setting

Fri, 17 Jul 2026 14:18:19 -0700 

On 7/17/26 09:20, Michael Walle wrote:

Before converting to the phylink interface, the init function would have
set a non-reserved I/F mode in the maccfg2 register. After converting to
phylink, 0 is written as mode, which is a reserved value (although it's
the hardware default). Without a valid mode, a SGMII link is never
established between the MAC and the PHY and thus .link_up() is never
called which could set the correct mode according to the actual speed.

Fix it by setting the maximum speed of the phy_interface_t in use in
.mac_config() - just like the driver did before the phylink conversion.

Fixes: 5d93cfcf7360 ("net: dpaa: Convert to phylink")
Suggested-by: Sean Anderson <[email protected]>
Signed-off-by: Michael Walle <[email protected]>
---
I didn't grab Sean's Rb tag as this is somewhat different.

Changes in v3:
  - keep the mode setting also in .adjust_link().
  - reword the commit message, to be (hopefully) more precise
  - Link to v2: 
https://lore.kernel.org/r/[email protected]/

Changes in v2:
  - the setting is/was based on the maximum speed, not the current
    speed. thus, move the setting into mac_config().
  - Link to v1: 
https://lore.kernel.org/r/[email protected]/

  .../net/ethernet/freescale/fman/fman_dtsec.c    | 17 ++++++++++++-----
  1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ethernet/freescale/fman/fman_dtsec.c 
b/drivers/net/ethernet/freescale/fman/fman_dtsec.c
index fe35703c509e..b8d70c0ecb6c 100644
--- a/drivers/net/ethernet/freescale/fman/fman_dtsec.c
+++ b/drivers/net/ethernet/freescale/fman/fman_dtsec.c
@@ -900,22 +900,28 @@ static void dtsec_mac_config(struct phylink_config 
*config, unsigned int mode,
  {
        struct mac_device *mac_dev = fman_config_to_mac(config);
        struct dtsec_regs __iomem *regs = mac_dev->fman_mac->regs;
-       u32 tmp;
+       u32 ecntrl, maccfg2;
+
+       maccfg2 = ioread32be(&regs->maccfg2);
+       maccfg2 &= ~(MACCFG2_NIBBLE_MODE | MACCFG2_BYTE_MODE);
switch (state->interface) { 
        case PHY_INTERFACE_MODE_RMII:
-               tmp = DTSEC_ECNTRL_RMM;
+               ecntrl = DTSEC_ECNTRL_RMM;
+               maccfg2 |= MACCFG2_NIBBLE_MODE;
                break;
        case PHY_INTERFACE_MODE_RGMII:
        case PHY_INTERFACE_MODE_RGMII_ID:
        case PHY_INTERFACE_MODE_RGMII_RXID:
        case PHY_INTERFACE_MODE_RGMII_TXID:
-               tmp = DTSEC_ECNTRL_GMIIM | DTSEC_ECNTRL_RPM;
+               ecntrl = DTSEC_ECNTRL_GMIIM | DTSEC_ECNTRL_RPM;
+               maccfg2 |= MACCFG2_BYTE_MODE;
                break;
        case PHY_INTERFACE_MODE_SGMII:
        case PHY_INTERFACE_MODE_1000BASEX:
        case PHY_INTERFACE_MODE_2500BASEX:
-               tmp = DTSEC_ECNTRL_TBIM | DTSEC_ECNTRL_SGMIIM;
+               ecntrl = DTSEC_ECNTRL_TBIM | DTSEC_ECNTRL_SGMIIM;
+               maccfg2 |= MACCFG2_BYTE_MODE;
                break;
        default:
                dev_warn(mac_dev->dev, "cannot configure dTSEC for %s\n",
@@ -923,7 +929,8 @@ static void dtsec_mac_config(struct phylink_config *config, 
unsigned int mode,
                return;
        }
- iowrite32be(tmp, &regs->ecntrl); 
+       iowrite32be(ecntrl, &regs->ecntrl);
+       iowrite32be(maccfg2, &regs->maccfg2);
  }
static void dtsec_link_up(struct phylink_config *config, struct phy_device *phy, 

Reviewed-by: Sean Anderson <[email protected]>

Christian, can you test this patch with ethernet at 100/1G speed if you still 
have
access to those P5020/P5040 boards?

https://lore.kernel.org/all/[email protected]/

Reply via email to