On Thu, Jul 30, 2026 at 4:53 PM Paul E. McKenney <[email protected]> wrote: > But is this really a fundamental RISC cost? For example, does arm64 > see the same performance issues?
We tested arm64 (Ampere Altra Max) with the same controlled experiment -- two 6.18 kernels, both voluntary, differing only in PREEMPT_DYNAMIC: Arch PREEMPT_DYNAMIC kill bogo-ops/sec Delta ------- --------------- ----------------- ----- ppc64le off 108,836 ppc64le on 68,197 -37.3% aarch64 off 5,538 aarch64 on 5,082 -8.2% arm64 sees -8.2% vs ppc64le's -37.3%. So arm64 is affected but much less severely. > In particular, I can see why the preempt_count() operations need to be > interrupt-safe, but I don't see why you would need barriers. And > doesn't powerpc still use software interrupt disabling? If so, why > not use that to simply software-disable interrupts around the > preempt_count() operations? > > What am I missing here? That's a good question -- I don't know enough about the powerpc preempt_count implementation to answer this. Shrikanth, could you comment on whether removing the barriers or using software interrupt disabling around preempt_count is feasible? Thank you Jirka
