rockchip_pcie_enable_l0s() is called from rockchip_pcie_host_init(), i.e. from the .init callback, which runs after the controller clocks and resets have been enabled. Replace the capability search with dw_pcie_get_pcie_cap(), which reads and caches the offset at this very point.
Reviewed-by: Shawn Lin <[email protected]> Signed-off-by: Hans Zhang <[email protected]> --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index bd86e32cc2b15..6d87da43cd6f0 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -374,7 +374,7 @@ static void rockchip_pcie_enable_l0s(struct dw_pcie *pci) u32 cap, lnkcap; /* Enable L0S capability for all SoCs */ - cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + cap = dw_pcie_get_pcie_cap(pci); if (cap) { lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); lnkcap |= PCI_EXP_LNKCAP_ASPM_L0S; -- 2.43.0
