Add device tree support for the WatchGuard Firebox T30 and T30-W. These devices are security appliances based on the Freescale P1020 SoC. They feature 5x Gigabit Ethernet ports, USB, and a serial console.
Signed-off-by: Lefteris Koutrakis <[email protected]> --- arch/powerpc/boot/dts/fsl/Makefile | 1 + arch/powerpc/boot/dts/fsl/firebox-t30.dts | 413 ++++++++++++++++++++++ 2 files changed, 414 insertions(+) create mode 100644 arch/powerpc/boot/dts/fsl/firebox-t30.dts diff --git a/arch/powerpc/boot/dts/fsl/Makefile b/arch/powerpc/boot/dts/fsl/Makefile index d2cc8e1f0..ebbf301e1 100644 --- a/arch/powerpc/boot/dts/fsl/Makefile +++ b/arch/powerpc/boot/dts/fsl/Makefile @@ -3,6 +3,7 @@ dtb-$(CONFIG_OF_ALL_DTBS) := $(patsubst $(src)/%.dts,%.dtb, $(wildcard $(src)/*.dts)) # MPC85xx platforms +dtb-$(CONFIG_MPC85xx_RDB) += firebox-t30.dtb dtb-$(CONFIG_BSC9131_RDB) += bsc9131rdb.dtb dtb-$(CONFIG_BSC9132_QDS) += bsc9132qds.dtb dtb-$(CONFIG_C293_PCIE) += c293pcie.dtb diff --git a/arch/powerpc/boot/dts/fsl/firebox-t30.dts b/arch/powerpc/boot/dts/fsl/firebox-t30.dts new file mode 100644 index 000000000..546e98938 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/firebox-t30.dts @@ -0,0 +1,413 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> + +/include/ "fsl/p1020si-pre.dtsi" + +/ { + model = "Watchguard Firebox T30"; + compatible = "watchguard,firebox-t30"; + + chosen { + bootargs-override = "console=ttyS0,115200 rw root=/dev/mmcblk0p2 rootfstype=squashfs rootwait"; + }; + + aliases { + label-mac-device = &enet0; + led-boot = &led0; + led-failsafe = &led1; + led-running = &led0; + led-upgrade = &led1; + }; + + memory { + device_type = "memory"; + }; + + cpus { + /delete-property/ PowerPC,P1020@1; + }; + + lbc: localbus@ffe05000 { + reg = <0 0xffe05000 0 0x1000>; + ranges = <0x0 0x0 0x0 0xefc00000 0x400000>; + + nor@0 { + compatible = "cfi-flash"; + reg = <0x0 0x0 0x400000>; + bank-width = <2>; + device-width = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x0 0x20000>; + label = "nor-cfg0"; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_nor_cfg0_1830: mac-address@1830 { + compatible = "mac-base"; + reg = <0x1830 0x11>; + #nvmem-cell-cells = <1>; + }; + + macaddr_nor_cfg0_1844: mac-address@1844 { + compatible = "mac-base"; + reg = <0x1844 0x11>; + #nvmem-cell-cells = <1>; + }; + + macaddr_nor_cfg0_1858: mac-address@1858 { + compatible = "mac-base"; + reg = <0x1858 0x11>; + #nvmem-cell-cells = <1>; + }; + + macaddr_nor_cfg0_186c: mac-address@186c { + compatible = "mac-base"; + reg = <0x186c 0x11>; + #nvmem-cell-cells = <1>; + }; + + macaddr_nor_cfg0_1880: mac-address@1880 { + compatible = "mac-base"; + reg = <0x1880 0x11>; + #nvmem-cell-cells = <1>; + }; + + macaddr_nor_cfg0_1894: mac-address@1894 { + compatible = "mac-base"; + reg = <0x1894 0x11>; + #nvmem-cell-cells = <1>; + }; + }; + }; + + partition@20000 { + reg = <0x20000 0x10000>; + label = "nor-cfg1"; + }; + + partition@30000 { + reg = <0x30000 0x20000>; + label = "nor-mfg"; + }; + + partition@50000 { + reg = <0x50000 0xc0000>; + label = "nor-bootopt"; + }; + + partition@110000 { + reg = <0x110000 0xc0000>; + label = "nor-extra1"; + }; + + partition@1d0000 { + reg = <0x1d0000 0xc0000>; + label = "nor-extra2"; + }; + + partition@290000 { + reg = <0x290000 0xe0000>; + label = "nor-backup"; + }; + + partition@370000 { + reg = <0x370000 0x10000>; + label = "nor-ubootenv"; + }; + + partition@380000 { + reg = <0x380000 0x80000>; + label = "nor-uboot"; + }; + }; + }; + }; + + soc: soc@ffe00000 { + ranges = <0x0 0x0 0xffe00000 0x100000>; + + i2c@3000 { + rtc@30 { + compatible = "sii,s35390a"; + reg = <0x30>; + }; + }; + + i2c@3100 { + tpm@29 { + compatible = "tpm,tpm_i2c_atmel"; + reg = <0x29>; + }; + }; + + sdhc@2e000 { + compatible = "fsl,p1020-esdhc", "fsl,esdhc"; + sdhci,auto-cmd12; + reg = <0x2e000 0x1000>; + interrupts = <0x48 0x2 0x0 0x0>; + interrupt-parent = <&mpic>; + fsl,sdhci-dma-broken; + fsl,sdhci-ahb2mag-irq-bypass; + fsl,sdhci-adjust-timeout; + clock-frequency = <0>; + }; + + spi0: spi@7000 { + compatible = "fsl,mpc8536-espi"; + reg = <0x7000 0x1000>; + interrupts = <0x3b 0x2>; + interrupt-parent = <&mpic>; + fsl,espi-num-chipselects = <4>; + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + compatible = "everspin,mr25h256", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x0 0x8000>; + label = "spi_mtd_0"; + }; + }; + }; + + slic@1 { + compatible = "zarlink,le88266"; + reg = <1>; + spi-max-frequency = <500000>; + }; + }; + + usb@22000 { + phy_type = "ulpi"; + dr_mode = "host"; + }; + + mdio@24000 { + switch0: switch@10 { + compatible = "marvell,mv88e6085"; + reg = <0x10>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch0phy0: ethernet-phy@0 { + reg = <0>; + }; + + switch0phy1: ethernet-phy@1 { + reg = <1>; + }; + + switch0phy2: ethernet-phy@2 { + reg = <2>; + }; + + switch0phy3: ethernet-phy@3 { + reg = <3>; + }; + + switch0phy4: ethernet-phy@4 { + reg = <4>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "wan"; + phy-handle = <&switch0phy0>; + nvmem-cells = <&macaddr_nor_cfg0_1830 0>; + nvmem-cell-names = "mac-address"; + }; + + port@1 { + reg = <1>; + label = "lan1"; + phy-handle = <&switch0phy1>; + nvmem-cells = <&macaddr_nor_cfg0_1844 0>; + nvmem-cell-names = "mac-address"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + phy-handle = <&switch0phy2>; + nvmem-cells = <&macaddr_nor_cfg0_1858 0>; + nvmem-cell-names = "mac-address"; + }; + + port@3 { + reg = <3>; + label = "lan3"; + phy-handle = <&switch0phy3>; + nvmem-cells = <&macaddr_nor_cfg0_186c 0>; + nvmem-cell-names = "mac-address"; + }; + + port@4 { + reg = <4>; + label = "lan4"; + phy-handle = <&switch0phy4>; + nvmem-cells = <&macaddr_nor_cfg0_1880 0>; + nvmem-cell-names = "mac-address"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&enet0>; + phy-mode = "rgmii-id"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + }; + + mdio@25000 { + status = "disabled"; + }; + + mdio@26000 { + status = "disabled"; + }; + + enet0: ethernet@b0000 { + phy-connection-type = "rgmii-id"; + rx-internal-delay-ps = <2000>; + tx-internal-delay-ps = <2000>; + nvmem-cells = <&macaddr_nor_cfg0_1830 0>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + enet1: ethernet@b1000 { + status = "disabled"; + }; + + enet2: ethernet@b2000 { + status = "disabled"; + }; + + gpio0: gpio-controller@fc00 { + }; + }; + + leds { + compatible = "gpio-leds"; + + led0: led-0 { + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_ORANGE>; + function = LED_FUNCTION_STATUS; + }; + + led1: led-1 { + gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_STATUS; + }; + + led2: led-2 { + gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_USB; + }; + + led3: led-3 { + gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_WLAN_5GHZ; + default-state = "keep"; + }; + + led4: led-4 { + gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_ORANGE>; + function = LED_FUNCTION_WLAN_2GHZ; + default-state = "keep"; + }; + + led5: led-5 { + gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_POWER; + default-state = "on"; + }; + }; + + pci0: pcie@ffe09000 { + reg = <0 0xffe09000 0 0x1000>; + ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; + status = "disabled"; + + pcie@0 { + ranges = <0x2000000 0x0 0xa0000000 + 0x2000000 0x0 0xa0000000 + 0x0 0x20000000 + + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x100000>; + }; + }; + + pci1: pcie@ffe0a000 { + reg = <0 0xffe0a000 0 0x1000>; + ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; + + pcie@0 { + ranges = <0x2000000 0x0 0x80000000 + 0x2000000 0x0 0x80000000 + 0x0 0x20000000 + + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x100000>; + + ath10k: wifi@0,0 { + reg = <0x0000 0 0 0 0>; + #gpio-cells = <2>; + gpio-controller; + nvmem-cells = <&macaddr_nor_cfg0_1894 0>; + nvmem-cell-names = "mac-address"; + }; + }; + }; +}; + +/include/ "fsl/p1020si-post.dtsi" -- 2.51.0
