On Tue, Nov 10, 2026 at 1:48 AM Marek Szyprowski <[email protected]> wrote: > > arch_dma_prep_coherent() is expected to remove any dirty cache lines > covering the buffer, so that they are neither lost nor evicted later on > top of data written through the uncached alias or by the device. > xtensa implements it with __invalidate_dcache_range(), which uses the > DHI instruction and discards dirty lines without writing them back. > > This loses data written through the cached kernel mapping right before > the call. dma_direct_alloc() zeroes the buffer with memset() on the > cached linear mapping and only then calls arch_dma_prep_coherent() and > switches to the KSEG bypass alias via arch_dma_set_uncached(). On cores > with a write-back data cache the zeroes still sitting in the cache are > dropped, and dma_alloc_coherent() returns a buffer with stale content. > > Use __flush_invalidate_dcache_range() (DHWBI) instead, which writes the > dirty lines back before invalidating them. On cores with a write-through > data cache it maps to __invalidate_dcache_range(), so nothing changes > there. > > Fixes: 0f665b9e2a6d ("xtensa: use the generic uncached segment support") > Signed-off-by: Marek Szyprowski <[email protected]> > --- > arch/xtensa/kernel/pci-dma.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Max Filippov <[email protected]> -- Thanks. -- Max
