Partial workaround for DTLB errata in MPC5121e processors of die M36P and older (all currently existing versions).
Due to the bug, the hardware-implemented LRU algorythm always goes to way 1 of the TLB. This fix forces writes to go to way 0, which would speed up memory-copy operations where bits 15...19 of source and destination address are the same. Signed-off-by: David Jander <da...@protonic.nl> --- arch/powerpc/kernel/head_32.S | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) --- a/arch/powerpc/kernel/head_32.S +++ b/arch/powerpc/kernel/head_32.S @@ -614,6 +614,14 @@ DataStoreTLBMiss: */ mfctr r0 /* Get PTE (linux-style) and check access */ +#ifdef CONFIG_PPC_MPC512x +/* MPC512x: (partial) workaround for errata in die M36P and earlier: + * Force writes to Way 0 (reads are always way 1) + */ + mfspr r3,SPRN_SRR1 + rlwinm r3,r3,0,15,13 /* Mask out SRR1[WAY] */ + mtspr SPRN_SRR1,r3 +#endif mfspr r3,SPRN_DMISS lis r1,page_off...@h /* check if kernel address */ cmplw 0,r1,r3 _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev