Hi all,
You are assuming the PCI memory space is prefetchable( no side effect)
for DMA. Is it possible that DMA is from non-prefetchable memory space?
This should be a safe assumption for this driver. Remember, this
driver just does offload memcpy, from one region to another. So the
PCI memory that you are reading from should be just a buffer of data,
and there should be side-effect of reading it.
However, I would like to see a comment at the top of the file warning
people that copying from PCI memory will result in prefetched reads.
Here's a few results from DMA tests between two
MPC8349EA boards housed in a CPCI chassis.
1. DMA mode register (DMAMRn)
PCI read command (PRC, bits 11:10)
a) DMAMRn[PRC] = 00 = PCI Read
The PCI read command is 6h on the PCI bus.
For DMA lengths of less than 1 cache line (32-bytes)
the DMA controller will generate a PCI 6h command.
However, for lengths of 32-bytes and higher, the
DMA controller actually generates a PCI Read Line (Eh)
command.
Freescale indicated that this 'change of PCI command code'
functionality is an undocumented 'feature', there to
improve performance for longer read lengths.
b) DMAMRn[PRC] = 01 = PCI Read Line
Generated the PCI command code for PCI read line (Eh),
regardless of DMA length.
c) DMAMRn[PRC] = 10 = PCI Read Multiple
Generated the PCI command code for PCI Read Multiple (Ch),
regardless of DMA length.
2. DMA from areas marked as non-prefetchable.
We setup two test cases:
a) Two boards in the same PCI segment with no intervening
bridges.
b) Two boards in separate PCI segments with intervening
bridges (in this case, there was two bridges on SBS
CPCI-to-CPI backplane bridging cards).
The PCI window to the IMMR registers on the boards is marked
as non-prefetchable. DMA from that area (reads) appeared on the
PCI bus as single 32-bit read transactions, i.e., the target
device effectively ignores the PCI read command, and the target
returns read data as single reads, i.e., the target acts as
as non-prefetchable memory.
We tested with the PCI Read Multiple command, and no data
was ever prefetched from the target. The bridges did not
prefetch and discard data, eg. we tried 36-bytes, and there
were 9 separate 4-byte transactions (we were using a 32-bit
PCI host for this test). Hence, at least for this example
target device, there are no side effects to using PCI
read multiple on the bus master, to a target PCI memory
region marked as non-prefetchable.
So even though the bridges were seeing transactions that
indicated read multiple, only single read cycles were
seen to be used.
Would you like some sort of summary of this info for a commit
message?
Would you like us to check any other transaction/register combos?
Cheers,
Dave
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