Here is a series of patches that implement some basic support for 64-bit Book3E processors that comply to architecture 2.06.
There is no specific processor announced yet. The patches make some shortcut which means they currently rely on an implementation that supports MMU v2 with support for the "HES" feature (HW entry select) and with support for the "TLB reservation" feature. They also assume a single unified TLB array. I shouldn't be very hard to implement support for other variants of the architecture on top of this though. The current set of patch has no proper support yet for hugetlb, nor for "special" interrupt levels (debug, critical and machine check). Some minimal support for debug/critical levels is provided specifically for the "Debug" interrupt (single step etc...) only when it occurs from within user space code. The intend is to merge these in 2.6.32. They rely on pretty much all the other patches I've been posting lately including the generic changes to add the virtual address argument to pte_free_tlb. v2. Various fixes, some addressing comments recieved and a whole bunch fixing other issues including breakage of existing platforms _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
