Benjamin,
Also, if you're going to access a PCI device directly, beware of other
issues such as ordering. PPC is an out of order architecture, you need
to ensure you add the appropriate memory barriers if you want to ensure
you accesses are done in the order you write them in your program.
For "standard" stuff that doesn't involve DMA or locks, an eieio after
both MMIO loads and stores should do the trick.
I'm not sure I understand. To clarify I have an FPGA connected via the PCI bus
which implements several peripherals, I've implemented device drivers for.
Currently I am calling ioremap() to get a virtual address corresponding to the
PCI devices. Then I use ___raw_writeN / ___raw_readN for reading/writing data
via the PCI bus to the FPGA registers. From looking at io.h I believe this
method is safe with regard to out of order execution.
"* ioremap is the standard one and provides non-cacheable guarded mappings
* and can be hooked by the platform via ppc_md "
Can you verify if my understanding is correct, or let me know if I need to add
memory barriers?
--
Best Regards,
________________________________________________________________
Eddie Dawydiuk, Technologic Systems | voice: (480) 837-5200
16525 East Laser Drive | fax: (480) 837-5300
Fountain Hills, AZ 85268 | web: www.embeddedARM.com
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