Benjamin Herrenschmidt <b...@kernel.crashing.org> wrote on 04/10/2009 22:28:38: > > > I have managed to update the TLB code to make proper use of dirty and > > accessed states. > > Advantages are: > > - I/D TLB Miss never needs to write to the linux pte, saving a few cycles > > That's good, that leaves us with only 40x to fix now. Also we can remove > atomic updates of PTEs for all non-hash. It's pointless on those CPUs > anyway. > > > - Accessed is only set by I/D TLB Error, should be a plus when SWAP is > > used. > > No need for that neither.
Since 8xx lacks HW support for ACCESSED, the only way is map the page NoAccess and take a TLB Error on first access that sets access bit (or bails to do_page_fault) > > ISI/DSI shouldn't touch the PTE. They should just fall back to C code > which takes care of it all.l Yes, that is what I do now(i.e I only read the pte). ISI and DSI is the TLB Miss handlers on 8xx. > > > - _PAGE_DIRTY is mapped to 0x100, the changed bit, and is set directly > > and there will be no extra DTLB Error to actually set the changed bit > > when a page has been made dirty. > > - Proper RO/RW mapping of user space. > > > > Cons: > > - 4 more insn in TLB Miss handlers, but the since the linux pte isn't > > written it should still be a win. > > > > However, I did this on my 2.4 tree but I can port it to 2.6 if you guys > > can test it for me. > > Why don't you use and test 2.6 ? :-) Because porting my 8xx board to 2.6 isn't going to be easy so I havn't yet. One day I might when we can't get away with 2.4 on our old boards. _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
