On Wed, 2009-10-28 at 19:09 +0530, Vineeth _ wrote: > Hi, > we are porting Linux 2.6.30 on a ppc440x5 based board. > when we check the kernel code in arch/powerpc/kernel/head_44x.S file @ > line number 162, > while creating the TLB for 256MB, the cache enable/disable property is > not set by the kernel ? or are we missing smthing ? > when we gave that particular attribute, things started working. Please > find the kernel code below. We added "PPC44x_TLB_I" attribute to set > the cache, kernel started working.
Ugh ? Why would you want to set I on the kernel memory ? I means "cache inhibited", which -disables- the cache. You really don't want that. You must have something else wrong. Cheers, Ben. > ----arch/powerpc/kernel/head_44x.S > > /* Load the kernel PID = 0 */ > li r0,0 > mtspr SPRN_PID,r0 > sync > > /* Initialize MMUCR */ > li r5,0 > mtspr SPRN_MMUCR,r5 > sync > > /* pageid fields */ > clrrwi r3,r3,10 /* Mask off the effective page number */ > ori r3,r3,PPC44x_TLB_VALID | PPC44x_TLB_256M > > /* xlat fields */ > clrrwi r4,r4,10 /* Mask off the real page number */ > /* ERPN is 0 for first 4GB page */ > > /* attrib fields */ > /* Added guarded bit to protect against speculative loads/stores */ > li r5,0 > ori r5,r5,(PPC44x_TLB_I|PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX > | PPC44x_TLB_G) > /* that cache thing u see above line is added by some malguns there's > some issue */ > > li r0,63 /* TLB slot 63 */ > > tlbwe r3,r0,PPC44x_TLB_PAGEID /* Load the pageid fields */ > tlbwe r4,r0,PPC44x_TLB_XLAT /* Load the translation fields */ > tlbwe r5,r0,PPC44x_TLB_ATTRIB /* Load the attrib/access fields */ > > --------- > > Is this can be considered as a good patch ? > > Thanks > Vineeth _ > _______________________________________________ > Linuxppc-dev mailing list > Linuxppc-dev@lists.ozlabs.org > https://lists.ozlabs.org/listinfo/linuxppc-dev _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
