Hi, Ben, 2009/12/7, Benjamin Herrenschmidt <b...@kernel.crashing.org>: > > Cache coherency bugs in the chipset or HW bugs in DBDMA, we've been > seeing those on/off on those old apple chipsets... > > Try forcing a 32 bytes alignment ? > You're thinking of placing the DMA descriptors on different cache lines?
That's excactly what I did with de2104x. But it was easier, I think. The chip handled its own DMA, and by writing a skip value to a register... I don't know this GC DMA controller well enough and haven't found the documentation either... But I tried the de21041 board with unmodified driver on this 7300, and it works. The problem was on a 5500. Risto _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
