Ira W. Snyder wrote:
I don't think this would break any existing hardware. The 83xx all
shares one IRQ line, and the 85xx/86xx only have per-channel interrupts,
right? (I'm not an 85xx/86xx guy, I've only got 83xx experience). This
is what the device trees suggest, anyway.
Right.
It looks like the other problem is that the controller interrupt handler
is assuming only one bit will be set in the summary register. It should
call the channel handler for each bit that is set.
Ok. I thought about doing this, but my changed approach seemed easier.
On the 83xx, we should only need to call the per-channel handler once
for each group of 8 bits. The original code used ffs(), which seems a
little wrong. Why call the handler twice if both EOSI and EOCDI are set
for a channel?
Sorry, I meant call it once per channel that has bits set.
Should I use a loop + mask, or is there some other neat
trick I can use?
After you process one channel, it shouldn't have any bits set (and if it
does, it's a new event that needs to be processed), so you could use the
current ffs approach with a while (summary reg != 0) loop around it.
Ok. All of the in-tree 83xx device trees have 5 interrupts listed. With
the changes described above, we'll only call request_irq() once in that
case, and use the per-controller interrupt.
I'll leave the documentation alone, with the exception of marking the
per-controller interrupt optional.
Hmm, that description is specific to 83xx, and such chips really should
have the controller interrupt specified. The per-channel interrupt
should not be optional, though.
-Scott
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