On Fri, Apr 16, 2010 at 12:38:43PM +0200, Peter Zijlstra wrote:
> On Thu, 2010-04-15 at 19:15 +0200, Frederic Weisbecker wrote:
> > > that looks rather ugly. Why not do a raw:
> > >
> > > this_cpu_inc(lockdep_stats.redundant_hardirqs_on);
> > >
> > > which basically open-codes debug_atomic_inc(), but without the warning?
> >
> >
> > Because that would open a race against interrupts that might
> > touch lockdep_stats.redundant_hardirqs_on too.
>
>
> How so, its a pure per-cpu variable right? so either the increment
> happens before the interrupts hits, or after, in either case there
> should not be a race with interrupts.
In x86 yeah, I guess the compiler simply loads the address
and does an inc directly, which is atomic wrt interrupts.
But what about another arch that would need an intermediate
load of the value:
load val, reg
add reg, 1
<---interrupt here
store reg, val
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