On Jun 16, 2010, at 1:58 AM, Micha Nelissen wrote: > Hi, > > Attached is a patch to fix large physical address support for the e500v2 > core. When >4GB addresses are used, the MAS7 register needs to be valid for > tlbsx instruction usage. > > Please review and apply. > > Micha > diff -u -ru linux-2.6.34/arch/powerpc/include/asm/reg.h > linux-2.6.34-fix/arch/powerpc/include/asm/reg.h > --- linux-2.6.34/arch/powerpc/include/asm/reg.h 2010-05-16 > 23:17:36.000000000 +0200 > +++ linux-2.6.34-fix/arch/powerpc/include/asm/reg.h 2010-06-16 > 08:43:28.000000000 +0200 > @@ -272,6 +272,7 @@ > #define HID0_DAPUEN (1<<8) /* Debug APU enable */ > #define HID0_SGE (1<<7) /* Store Gathering Enable */ > #define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */ > +#define HID0_EN_MAS7_UPDATE (1<<7) /* tlbre/tlbsx update MAS7 - e500v2 > */ > #define HID0_DCFA (1<<6) /* Data Cache Flush Assist */ > #define HID0_LRSTK (1<<4) /* Link register stack - 745x */ > #define HID0_BTIC (1<<5) /* Branch Target Instr Cache Enable */ > diff -u -ru linux-2.6.34/arch/powerpc/kernel/head_fsl_booke.S > linux-2.6.34-fix/arch/powerpc/kernel/head_fsl_booke.S > --- linux-2.6.34/arch/powerpc/kernel/head_fsl_booke.S 2010-05-16 > 23:17:36.000000000 +0200 > +++ linux-2.6.34-fix/arch/powerpc/kernel/head_fsl_booke.S 2010-06-16 > 08:45:10.000000000 +0200 > @@ -328,6 +328,13 @@ > oris r2,r2,hid0_d...@h > mtspr SPRN_HID0, r2 > #endif > +#ifdef CONFIG_PTE_64BIT > +BEGIN_MMU_FTR_SECTION > + mfspr r2,SPRN_HID0 > + ori r2,r2,hid0_en_mas7_upd...@l > + mtspr SPRN_HID0, r2 > +END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS) > +#endif
If you want to do this, do it in: arch/powerpc/kernel/cpu_setup_fsl_booke.S - k _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
