On Thu, Jul 08, 2010 at 11:01:11AM -0500, Lee Nipper wrote: >On Thu, Jul 8, 2010 at 10:06, Marc Chidester <[email protected]> wrote: >> It looks like the Rev D version of the 405EX chip without security >> will be identified as a 405EXr, based on the values in the cpu_specs >> table. For 405EX/405EXr the pvr_mask is 0xffff0004 with the >> pvr_value's as 0x12910004 and 0x12910000 respectively. I see that the >> Rev D PVR value for the 405EX without security is 0x12911473, which >> would mask out to the EXr value. >> >> Is there an algorithm update needed or am I missing something? > >With 405EX Rev D, we have noticed that we must reset our board >one time after the initial powerup to make the PVR read correctly. > >See this post: >http://lists.ozlabs.org/pipermail/linuxppc-dev/2009-December/079099.html
That is very very weird. Have you seen that behavior on multiple Rev D CPUs or just one board or? The PVR value should never change, so if you have odd behavior I wonder if the are silicon bugs in that revision. Did you happen to ask AMCC about it? josh _______________________________________________ Linuxppc-dev mailing list [email protected] https://lists.ozlabs.org/listinfo/linuxppc-dev
