> From: Shaohui Xie [mailto:b21...@freescale.com]
>
> The sRIO controller reports errors to the core with one signal, it
uses
> register EPWISR to provides the core quick access to where the error
occurred.
> The EPWISR indicates that there are 4 interrupts sources, port1,
port2, message
> unit and port write receive, but the sRIO driver does not support
port2
> for now, still the handler takes care of port2.
> Currently the handler only clear error status without any recovery.
>
Do these dual-RIO controllers have only one port-write interrupt?
(sorry, user manuals are not available for download from FSL).
> @@ -1082,14 +1142,24 @@ fsl_rio_port_write_handler(int irq, void
*dev_instance)
> ipwsr = in_be32(&priv->msg_regs->pwsr);
>
> epwisr = in_be32(priv->regs_win + RIO_EPWISR);
> - if (epwisr & 0x80000000) {
> + if (epwisr & EPWISR_ERR_PINT1) {
> tmp = in_be32(priv->regs_win + RIO_LTLEDCSR);
> pr_info("RIO_LTLEDCSR = 0x%x\n", tmp);
> - out_be32(priv->regs_win + RIO_LTLEDCSR, 0);
> + port_error_handler(port, 0);
> + }
> +
> + if (epwisr & EPWISR_ERR_PINT2) {
> + pr_info("RIO: port2 error\n");
> + port_error_handler(port, 1);
> + }
> +
> + if (epwisr & EPWISR_ERR_MU) {
> + pr_info("RIO: message unit error\n");
> + msg_unit_error_handler(port);
> }
>
> - if (!(epwisr & 0x00000001))
> - return IRQ_HANDLED;
> + if (!(epwisr & EPWISR_ERR_PW))
> + return IRQ_NONE;
>
> #ifdef DEBUG_PW
> pr_debug("PW Int->IPWMR: 0x%08x IPWSR: 0x%08x (", ipwmr, ipwsr);
This part is out of sync with mainline code tree (37-rc1). Probably it
should be updated to make it easier to apply your patch. Besides that,
works as expected on my RIO setup.
Regards,
Alex.
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