O> +void dwc_otg_flush_rx_fifo(struct core_if *core_if)
> +{
> + ulong global_regs = core_if->core_global_regs;
These are all a bit odd. The register has a given size so they ought to
be u32 or u64 etc as appropriate for the register in question, ditto the
cache in the structure.
> + for (i = 0; i < MAX_EPS_CHANNELS; i++) {
> + offset = i * DWC_EP_REG_OFFSET;
> +
> + dev_if->in_ep_regs[i] = (ulong)(reg_base +
> + DWC_DEV_IN_EP_REG_OFFSET +
> + offset);
And again some of the casting seems odd. If these are bus addresses they
should be typed as such.
> +static inline u32 dwc_reg_read(ulong reg , u32 offset)
> +{
> +
> +#ifdef CONFIG_DWC_OTG_REG_LE
> + return in_le32((void __iomem *)(reg + offset));
> +#else
> + return in_be32((void __iomem *)(reg + offset));
All this casting is a symptom of the same typing problems. They would all
go away if the types were right in the first place.
> + u32 global_regs = (u32) core_if->core_global_regs;
And again we keep finding these casts caused by wrong types
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