On Wed, Jun 06, 2012 at 01:26:16PM -0500, Scott Wood wrote: > On 06/06/2012 04:31 AM, Zhao Chenhui wrote: > > On Tue, Jun 05, 2012 at 11:07:41AM -0500, Scott Wood wrote: > >> On 06/05/2012 04:08 AM, Zhao Chenhui wrote: > >>> On Fri, Jun 01, 2012 at 10:40:00AM -0500, Scott Wood wrote: > >>>> I know you say this is for dual-core chips only, but it would be nice if > >>>> you'd write this in a way that doesn't assume that (even if the > >>>> corenet-specific timebase freezing comes later). > >>> > >>> At this point, I have not thought about how to implement the > >>> cornet-specific timebase freezing. > >> > >> I wasn't asking you to. I was asking you to not have logic that breaks > >> with more than 2 CPUs. > > > > These routines only called in the dual-core case. > > Come on, you know we have chips with more than two cores. Why design > such a limitation into it, just because you're not personally interested > in supporting anything but e500v2? > > Is it so hard to make it work for an arbitrary number of cores? > > >>> If do not set them, it may make KEXEC fail on other platforms. > >> > >> What platforms? > > > > Such as P4080, P3041, etc. > > So we need to wait for corenet timebase sync before we stop causing > problems in virtualization, simulators, etc. if a kernel has kexec or > cpu hotplug enabled (whether used or not)? > > Can you at least make sure we're actually in a kexec/hotplug scenario at > runtime? > > Or just implement corenet timebase sync -- it's not that different. > > -Scott
We also work on the corenet timebase sync. Our plan is first the dual-core case, then the case of more than 2 cores. We will submit the corenet timebase sync patch soon. -Chenhui _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
