On Mar 21, 2012, at 11:54 PM, Prabhakar Kushwaha wrote: > BSC9131RDB is a Freescale reference design board for BSC9131 SoC.The BSC9131 > is integrated SoC that targets Femto base station market. It combines Power > Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F > baseband acceleration processing elements. > > The BSC9131 SoC includes the following function and features: > . Power Architecture subsystem including a e500 processor with 256-Kbyte > shared L2 cache > . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache > . The Multi Accelerator Platform Engine for Femto BaseStation Baseband > Processing (MAPLE-B2F) > . A multi-standard baseband algorithm accelerator for Channel > Decoding/Encoding, Fourier Transforms, UMTS chip rate processing, LTE > UP/DL Channel processing, and CRC algorithms > . Consists of accelerators for Convolution, Filtering, Turbo Encoding, > Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix > Inversion operations > . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit > with ECC, up to 400-MHz clock/800 MHz data rate > . Dedicated security engine featuring trusted boot > . DMA controller > . OCNDMA with four bidirectional channels > . Interfaces > . Two triple-speed Gigabit Ethernet controllers featuring network > acceleration including IEEE 1588. v2 hardware support and > virtualization (eTSEC) > . eTSEC 1 supports RGMII/RMII > . eTSEC 2 supports RGMII > . High-speed USB 2.0 host and device controller with ULPI interface > . Enhanced secure digital (SD/MMC) host controller (eSDHC) > . Antenna interface controller (AIC), supporting three industry standard > JESD207/three custom ADI RF interfaces (two dual port and one single > port) and three MAXIM's MaxPHY serial interfaces > . ADI lanes support both full duplex FDD support and half duplex TDD > support > . Universal Subscriber Identity Module (USIM) interface that facilitates > communication to SIM cards or Eurochip pre-paid phone cards > . TDM with one TDM port > . Two DUART, four eSPI, and two I2C controllers > . Integrated Flash memory controller (IFC) > . TDM with 256 channels > . GPIO > . Sixteen 32-bit timers > > The DSP portion of the SoC consists of DSP core (SC3850) and various > accelerators pertaining to DSP operations. > > BSC9131RDB Overview > ---------------------- > BSC9131 SoC > 1Gbyte DDR3 (on board DDR) > 128Mbyte 2K page size NAND Flash > 256 Kbit M24256 I2C EEPROM > 128 Mbit SPI Flash memory > USB-ULPI > eTSEC1: Connected to RGMII PHY > eTSEC2: Connected to RGMII PHY > DUART interface: supports one UARTs up to 115200 bps for console display > > Linux runs on e500v2 core and access some DSP peripherals like AIC > > Signed-off-by: Ramneek Mehresh <ramneek.mehr...@freescale.com> > Signed-off-by: Priyanka Jain <priyanka.j...@freescale.com> > Signed-off-by: Akhil Goyal <akhil.go...@freescale.com> > Signed-off-by: Poonam Aggrwal <poonam.aggr...@freescale.com> > Signed-off-by: Rajan Srivastava <rajan.srivast...@freescale.com> > Signed-off-by: Prabhakar Kushwaha <prabha...@freescale.com> > ---
applied to next. (Made some minor changes to match upstream board ports like p1010, also sorted Makefile & Kconfig by Alphabet) - k _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
