Phileas Fogg <phileas-f...@mail.ru> writes: > And another note. > I took a look at the MMU chapter in the Cell Architecture handbook and indeed > the first 15 bits in VA are treated as 0 by the hardware. > > Quote: > > 1. High-order bits above 65 bits in the 80-bit virtual address (VA[0:14]) are > not implemented. The hardware always > treats these bits as `0'. Software must not set these bits to any other > value than `0' or the results are undefined in > the PPE. > >
True, we missed the below part of ISA doc: ISA doc says "On implementations that support a virtual address size of only n bits, n < 78, bits 0:77-n of the AVA field must be zeros. " The Cell document I found at https://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/7A77CCDF14FE70D5852575CA0074E8ED/$file/CellBE_Handbook_v1.12_3Apr09_pub.pdf gives Virtual Address (VA) Size -> 65 bits So as per ISA, bits 0:12 should be zero, which should make 0:14 of PTE fields zero for Cell. I will try to do a patch. Thanks for debugging this. -aneesh _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
