On 05/09/2013 07:37:42 AM, Benjamin Herrenschmidt wrote:
On Thu, 2013-05-09 at 17:44 +0800, tiejun.chen wrote:
>
> Actually in the case GS=1 even if EE=0, EXT/DEC/DBELL still occur
as I
> recall.
Only if directed to the hypervisor.
This is always the case with KVM, right? At least on booke...
> > Case 1)
> > -> Local_irq_disable() will set soft_enabled = 0
> > -> Now Externel interrupt happens, there we set PACA_IRQ_EE in
> irq_happened, Also clears EE in SRR1 and rfi. So interrupts are hard
> disabled. No more other interrupt gated by MSR.EE can happen. Looks
> like the idea here is to not let a device keep on inserting
interrupt
> till the interrupt condition on device is cleared, right?
The external interrupt line is level sensitive normally, so we have to
mask MSR:EE in that case or the interrupt would keep re-occurring
(note
that FSL has this concept of auto-acked interrupts via the on die MPIC
for which you can potentially use PACA_IRQ_EE_EDGE instead and avoid
having to mask MSR:EE).
Note that if we do this, we can no longer leave the interrupt vector in
EPR, and would have to track (potentially multiple different) pending
external interrupts in software.
-Scott
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