> >> /* > >> * For the 8xx processors, all of them report the same PVR family for > >> * the PowerPC core. The various versions of these processors must be > >> diff -- git a/arch/powerpc/include/asm/reg_booke.h > >> b/arch/powerpc/include/asm/reg_booke.h > >> index ed8f836..4a6457e 100644 > >> --- a/arch/powerpc/include/asm/reg_booke.h > >> +++ b/arch/powerpc/include/asm/reg_booke.h > >> @@ -170,6 +170,7 @@ > >> #define SPRN_L2CSR1 0x3FA /* L2 Data Cache Control and Status > Register 1 > >> */ > >> #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ > >> #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register > */ > >> +#define SPRN_PWRMGTCR0 0x3FB /* Power management control register > 0 */ > > > > Is this generic for booke or e6500 specific? I can't see this register > either in ISA and EREF.
Yes, now only e6500 have this register. There is no problem in this definition, because no conflict in FSL platform. > > Also I can see SPRN_ICCR also with same SPRN, how that is possible? > > Its possibly because the register maybe in implementation specific region. > I'm guessing ICCR is a 40x specific register. Yes, kumar is right. Its use only in 4xx series of chips. ICTC(arch/powerpc/include/asm/reg.h) also use 0x3FB, Its use only in 6xx series of chips. -dongsheng _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
