Hi Anatolij, we have tried again… but the problem is still there… we are not able to read/write, not only CS4, but also CS1, CS2, CS3, etc…
According to you, could we fix the problem if we include our Virtex FPGA in Device Tree? U-Boot has been patched (not by us), for CS4, with: +#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE +#define CONFIG_SYS_CS0_CFG 0x000ADD00 +#define CONFIG_SYS_CS3_START 0x10000000 // +#define CONFIG_SYS_CS3_SIZE 0x00020000 // +#define CONFIG_SYS_CS3_CFG 0x0002DF00 // + +#define CONFIG_SYS_CS4_START 0x10020000 // +#define CONFIG_SYS_CS4_SIZE 0x00020000 // +#define CONFIG_SYS_CS4_CFG 0x0002DC00 // + +#define CONFIG_SYS_CS5_START 0x11000000 // +#define CONFIG_SYS_CS5_SIZE 0x01000000 // +#define CONFIG_SYS_CS5_CFG 0x0002DD00 // + +#define CONFIG_SYS_CS_BURST 0x00000000 +#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 + +#define CONFIG_SYS_RESET_ADDRESS 0xff000000 but CONFIG_SYS_CS4_SIZE should be: 0x00010000 ... Thank you Lorenzo On 19/nov/2013, at 10:45 PM, Anatolij Gustschin <ag...@denx.de> wrote: > Hi Lorenzo, > > On Tue, 19 Nov 2013 11:20:24 +0100 > neorf3k <neor...@gmail.com> wrote: > >> Hello Anatolij, this is our code, used at University, but again it doesn’t >> work… >> >> How i told, the only information we have about that reg are: >> >> Chip select 4 specification: >> Lp_cs4 >> bus size: 8 bit >> bus control: 2 wait state R/W ACK disabled >> size allocated: 4 KByte >> >> Our Register 8 bit LP_cs4 (we want to write) >> >> cs4 offset: 0x001 > > is the byte in FPGA at offset 0x0 writable? In your code you > currently test read/write access to the byte at offset 0x0. > > If the read/write access works under U-Boot, then maybe the > chip select parameters for CS4 are configured differently > in U-Boot. You can dump the Chip Select 4 configuration > registers under U-Boot and compare. Is address- and data-bus > to the FPGA multipexed? Another possible reason for non-working > access could be that the configured CS4 range 0x10020000 - 0x10030000 > overlaps with configured range for CS0, CS1, CS2 or CS3. Can you > verify that no such overlapping exists. > > Thanks, > > Anatolij _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev