On Fri, Feb 07, 2014 at 04:18:47PM +0100, Peter Zijlstra wrote:
> On Fri, Feb 07, 2014 at 01:28:37PM +0100, Peter Zijlstra wrote:
> > Anyway, you can do a version with lwarx/stwcx if you're looking get rid
> > of lharx.
>
> the below seems to compile into relatively ok asm. It can be done better
> if you write the entire thing by hand though.
[...]
>
> static inline unsigned int xadd(unsigned int *v, unsigned int i)
> {
> int t, ret;
>
> __asm__ __volatile__ (
> "1: lwarx %0, 0, %4\n"
> " mr %1, %0\n"
> " add %0, %3, %0\n"
> " stwcx. %0, %0, %4\n"
> " bne- 1b\n"
> : "=&r" (t), "=&r" (ret), "+m" (*v)
> : "r" (i), "r" (v)
> : "cc");
>
> return ret;
> }
>
I don't like this xadd thing -- it's so x86 ;)
x86 has its LOCK prefix, ppc has ll/sc.
That should be reflected somehow IMHO.
Maybe if xadd became mandatory for some kernel library.
>
> void ticket_unlock(tickets_t *lock)
> {
> ticket_t tail = lock->tail + 1;
>
> /*
> * The store is save against the xadd for it will make the ll/sc fail
> * and try again. Aside from that PowerISA guarantees single-copy
> * atomicy for half-word writes.
> *
> * And since only the lock owner will ever write the tail, we're good.
> */
> smp_store_release(&lock->tail, tail);
> }
Yeah, let's try that on top of v2 (just posted).
First, I want to see v2 work as nicely as v1 --
compiling a debug kernel takes a while...
Torsten
_______________________________________________
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
