On Tue, 2014-04-15 at 15:43 +0800, Dongsheng Wang wrote: > From: Wang Dongsheng <dongsheng.w...@freescale.com> > > Root cause is pcie power management state transition need a delay. > The delay time define in "PCI Bus Power Management Interface Specification". > > D0, D1 or D2 --> D3 need to delay 10ms. > D3 --> D0 need to delay 10ms. > > Signed-off-by: Wang Dongsheng <dongsheng.w...@freescale.com>
Could you describe the other changes besides the addition of a delay at the end? -Scott _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
