From: Madhavan Srinivasan > This patchset create the infrastructure to handle the CR based > local_* atomic operations. Local atomic operations are fast > and highly reentrant per CPU counters. Used for percpu > variable updates. Local atomic operations only guarantee > variable modification atomicity wrt the CPU which owns the > data and these needs to be executed in a preemption safe way.
These are usually called 'restartable atomic sequences (RAS)'. > Here is the design of the first patch. Since local_* operations > are only need to be atomic to interrupts (IIUC), patch uses > one of the Condition Register (CR) fields as a flag variable. When > entering the local_*, specific bit in the CR5 field is set > and on exit, bit is cleared. CR bit checking is done in the > interrupt return path. If CR5[EQ] bit set and if we return > to kernel, we reset to start of local_* operation. I don't claim to be able to read ppc assembler. But I can't see the code that clears CR5[EQ] for the duration of the ISR. Without it a nested interrupt will go through unwanted paths. There are also a lot of 'magic' constants in that assembly code. I also wonder if it is possible to inspect the interrupted code to determine the start/end of the RAS block. (Easiest if you assume that there is a single 'write' instruction as the last entry in the block.) Also, how expensive is it to disable all interrupts? David _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev