Le 04/09/2015 18:43, Scott Wood a écrit :
On Thu, Sep 03, 2015 at 11:27:03AM +0200, Christophe Leroy wrote:
On PPC832x, perf record/report reports martian addresses
2.62% perf_reseau4 libpthread-2.18.so [.] __libc_send
2.56% perf_reseau4 [kernel.kallsyms] [k] __ip_make_skb
1.62% perf_reseau4 [kernel.kallsyms] [k] __ip_append_data.isra.39
1.55% perf_reseau4 [kernel.kallsyms] [k] ip_finish_output
1.33% perf_reseau4 [unknown] [k] 0x7ffffd94
1.33% perf_reseau4 [unknown] [k] 0x7ffffd95
1.28% perf_reseau4 [unknown] [k] 0x7ffffd97
1.26% perf_reseau4 [unknown] [k] 0x7ffffda3
1.24% perf_reseau4 [unknown] [k] 0x7ffffd98
1.22% perf_reseau4 [unknown] [k] 0x7ffffd92
1.22% perf_reseau4 [unknown] [k] 0x7ffffd9b
[.....]
This is due to function perf_instruction_pointer() reading SPR SIAR
which doesn't exist on e300 core. The perf_instruction_pointer() is
redefined in arch/powerpc/perf/core-book3s.c when CONFIG_PPC_PERF_CTRS
is selected.
This patch moves the selection of CONFIG_PPC_HAVE_PMU in 86xx section
so that CONFIG_PPC_PERF_CTRS won't be selected for other 6xx powerpc
Signed-off-by: Christophe Leroy <christophe.le...@c-s.fr>
So, what happens when a kernel is built that supports both 83xx and 86xx?
Right, so should we define a processor feature for it ?
Plus, it's e300, not e600, that is the exception among 6xx-style cores.
Is it ? I've been looking for special register SIAR (spr 955) in several
6xx reference manuals.
82xx doesn't have it, 52xx and 512x don't have it.
I found it only in the 86xx
Which other family has it ?
Christophe
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