Grant Likely wrote: > On 5/1/07, John Williams <[EMAIL PROTECTED]> wrote: > >> Grant Likely wrote: >> > However, the uartlite is *not* an 8250. The 8250 turns up all over >> > the place and it's registers are defined as 8 bit wide. The >> > offset-by-3 stuff is part of the plat_serial8250_port structure which >> > is also used to specify .regshift (increment between registers). >> > Whereas the UARTLITE is defined as a 32 bit device and it doesn't show >> > up in anywhere near as many designs. Registers are always 4 bytes >> > wide and are always located at multiples of 4 bytes off the base > > Hmm, I think I was smoking something last night. Address used for 8 > bit access should not be affected by CPU endianess. After David's > comments, I reread the uartlite documentation. The current design is > definately for 32bit OPB bus connections, but it looks like there is a > posibility for xilinx to add a 16 or 8 bit attachment. Since the > uartlite design explicitly supports 8, 16 and 32 bit access, sticking > with 8 bit io may be the safest.
To be honest I don't think that will ever happen - just because the OPB bus data width is parameterisable, doesn't mean that it actually *works* or has been tested on anything other than 32-bits wide. I've certainly never heard of anyone doing so, on either MicroBlaze or PPC. but, I won't fight over it :) Either way, it will still require a code change if/when someone does a 16/8 bit wide OPB bus. Whether they change the IO access operation, or a hardcoded constant, it's still not perfect. Of course the real solution here is to create an OPB bus driver, with a 'width' field that you can pull out of XPAR, and so on... Use that instead of platform bus, and all this rubbish can be dealt with cleanly. > However, I still think the > application of the 3 byte offset should be done in the driver, and not > in the platform bus registration. If it has to be done, I agree the driver is the place to put it. > I've reworked the patch with the following changes > - remove 3 byte offset from platform bus registration. > - added ulite_in/ulite_out macros to make changing bus attachment > details simpler if xilinx changes the uartlite design. > - stick with 8 bit IO. It works fine, however perhaps a comment explaining the +3 offset might be appreciated by those who follow. > Tested on PPC. John, can you please test on microblaze? Acked-by: John Williams <[EMAIL PROTECTED]> John _______________________________________________ Linuxppc-embedded mailing list [email protected] https://ozlabs.org/mailman/listinfo/linuxppc-embedded
