hi all: I have been working on my pci for about 2 mounths ,but I can't work it out. I list the problems I encounter here.Any suggestion will be welcome. We want to send 208 bytes per frame.but it was send in several frames. We try to disalbe the snoop bit in our program ,choose another dma band width.the result it we can speed up the speed ,but it can't be checked through by our check program.what confused us is that the data gets by our software transferes through the hardware is right . some one suggests that: When snooping is not used and a memeory region is cacheable, you should invalidate cache area (executing as much DCBI instructions as required) corresponding to the transfer region after each transfer before read it by the core. Refer to the Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture, Chapter 8 Instruction Set, dcbi.
our Latency Timer Register value is 0xc4,and the cachline is 0x8 thank you for you attention. feng _______________________________________________ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded
