Mark,
>
> I haven't been following this closely, but are you sure it's a WDT
> reset? You can tell from the Reset Status Register (RSR).
> u-boot prints out a decode of this register, which also clears the
> bits, so you have to go by the printout when u-boot starts to see
> why the last reset occurred.
U-boot is reporting the Watchdog reset. You can see:
U-Boot 1.1.4 (Apr 11 2006 - 14:39:01)
MPC8272 Reset Status: Software Watchdog, External Soft, External Hard
MPC8272 Clock Configuration
- Bus-to-Core Mult 4x, VCO Div 2, 60x Bus Freq 25-75 , Core Freq 100-300
- dfbrg 1, corecnf 0x1a, busdf 3, cpmdf 1, plldf 0, pllmf 3
- vco_out 400000000, scc_clk 100000000, brg_clk 25000000
- cpu_clk 400000000, cpm_clk 200000000, bus_clk 100000000
- pci_clk 66666666
CPU: MPC8272 (HiP7 Rev 14, Mask 1.0 1K50M) at 400 MHz
Board: Televes XXX8248
Watchdog enabled
>
> Just trying to help brainstorm...
>
> Mark Chambers
>
Thanks,
Alex Bastos
