Alex Zeffertt wrote: >Hi Kalle, I've just checked and it makes no difference to the ATM >driver. In fact, on my platform (PM828+u-boot-1.1.3) the pipeline >depth was already set to 1. > >You are probably right that the pipeline depth was the cause of your >problem- but my problem is something else. I think that Freescale >simply overlooked the ATM external connection table case when >designing the cache coherency protocol - because they offered no way >to assert GBL when external connection tables are accessed. > > The ATM in 8260 seems to have a huge errata list. Just quickly looking at those at least CPM71: CPM does not snoop MCC buffer descriptors sounds related, but it may be some other issue also. Do you already use the microcode patch provided by Freescale?
I'm confident my problem was fixed with the correct setting of the pipeline depth. I had trouble with everything related to cache coherency, not just a single communication protocol.
