David H. Lynch Jr wrote:
I am working through bringing up Linux 2.6.14 on a Xilinx V4 based
ppc405. with memory from 0x0 through 0x7fffffff
I get to this point in head_4xx.S:
/* We now have the lower 16 Meg mapped into TLB entries, and the caches
* ready to work.
*/
turn_on_mmu:
lis r0,MSR_KERNEL at h
ori r0,r0,MSR_KERNEL at l
mtspr SPRN_SRR1,r0
lis r0,start_here at h // SPRN_SRR0 is where the rfi
resumes execution
ori r0,r0,start_here at l
mtspr SPRN_SRR0,r0
SYNC
rfi /* enables MMU */
b . /* prevent prefetch past rfi */
The value of SPRN_SRRO is 0xffffc00000002218 and SPRN_SRR1 is
0x0000000200001032
I have not checked the bits in SPRN_SRR1 but isn't 0xffffc00000002218
wrong ? it looks like it was sign
extended. physical 0x2218 is start_here so that part is corect.
